US 12,224,315 B2Granted

Semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorsJu Hun Park, Won Cheol Jeong, Jin Wook Kim, Deok Han Bae, Myung Yoon Um, In Yeal Lee, Yoon Young Jung

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor device includes an active pattern extending in a first direction on a substrate, a gate structure on the active pattern and having a gate electrode extending in a second direction intersecting the active pattern, and a gate capping pattern on the gate electrode, the gate capping pattern including a gate capping liner defining a gate capping recess, the gate capping liner having a horizontal portion along an upper surface of the gate electrode, and a vertical portion extending from the horizontal portion in a third direction intersecting the first and second directions, and a gate capping filling film on the gate capping liner and filling the gate capping recess, an epitaxial pattern on the active pattern and adjacent the gate structure, a gate contact on and connected to the gate electrode, and an active contact on and connected to the epitaxial pattern.

Claims20

Dependent claims

A semiconductor device, comprising:

an active pattern extending in a first direction on a substrate;
a first gate structure on the active pattern, the first gate structure including:
a first gate electrode intersecting the active pattern, the first gate electrode extending in a second direction intersecting the first direction, and
a first gate capping pattern on the first gate electrode, the first gate capping pattern including:
a first lower gate capping liner defining a first gate capping recess, the first lower gate capping liner having a first horizontal portion extending along an upper surface of the first gate electrode, and a first vertical portion extending from the first horizontal portion in a third direction intersecting the first direction and the second direction, and
a first gate capping filling film on the first lower gate capping liner and filling the first gate capping recess;
a second gate structure extending in the second direction, the second gate structure being spaced apart from the first gate structure in the first direction;
a first epitaxial pattern on the active pattern, the first epitaxial pattern being between the first gate structure and the second gate structure;
a gate contact on and connected to the first gate electrode, wherein the first gate capping filing film is disposed in a space between the first lower gate capping liner and the gate contact;
and
a first active contact on and connected to the first epitaxial pattern.

8 more elements

A semiconductor device, comprising:

an active pattern extending in a first direction on a substrate;
a first gate structure on the active pattern, the first gate structure including:
a first gate electrode intersecting the active pattern, the first gate electrode extending in a second direction intersecting the first direction, and
a first gate capping pattern on the first gate electrode, the first gate capping pattern including:
a first lower gate capping liner defining a first gate capping recess, and
a first gate capping filling film on the first lower gate capping liner, the first gate capping filling film filling the first gate capping recess;
a second gate structure extending in the second direction, the second gate structure being spaced apart from the first gate structure in the first direction;
a first epitaxial pattern on the active pattern, the first epitaxial pattern being between the first gate structure and the second gate structure;
a first active contact on and connected to the first epitaxial pattern, the first lower gate capping liner being on a part of side walls of the first active contact and extending to an upper surface of the first active contact;
and
a gate contact on and connected to the first gate electrode, wherein the first gate capping filing film is disposed in a space between the first lower gate capping liner and the gate contact.

8 more elements

A semiconductor device, comprising:

an active pattern extending in a first direction on a substrate;
a first gate structure on the active pattern, the first gate structure including:
a first gate electrode intersecting the active pattern, the first gate electrode extending in a second direction intersecting the first direction, and
a first gate capping pattern on the first gate electrode, the first gate capping pattern including a first gate capping liner defining a first gate capping recess, and a first gate capping filling film on the first gate capping liner and filling the first gate capping recess;
a second gate structure extending in the second direction, the second gate structure being spaced apart from the first gate structure in the first direction;
a third gate structure extending in the second direction, the third gate structure being spaced apart from the second gate structure in the first direction, and the second gate structure being between the first gate structure and the third gate structure;
a first epitaxial pattern on the active pattern, the first epitaxial pattern being between the first gate structure and the second gate structure;
a second epitaxial pattern on the active pattern, the second epitaxial pattern being between the second gate structure and the third gate structure;
a gate contact on and connected to the first gate electrode;
a first active contact on and connected to the first epitaxial pattern, a lower surface of the gate contact being higher than an upper surface of the first active contact;
and
a second active contact on and connected to the second epitaxial pattern.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/516,900Filed 2 Nov 2021
Priority: KR 10-2021-00172798 Feb 2021
Published: US 2022/0254881 A111 Aug 2022
Granted: 11 Feb 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 62/118
Shapes of semiconductor bodies: nanostructure semiconductor bodies
H10D 62/121
Nanowire, nanosheet or nanotube semiconductor bodies: oriented parallel to substrates
H10D 30/501
Field-effect transistors [FET]: fETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers

Family

US 2022/0254881 A1Pre-grant publication · published 11 Aug 2022
US 12,224,315 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key