Size-controllable multi-stack semiconductor device and method of manufacturing the same

A multi-stack semiconductor device comprising:

• a substrate;
• and
• a plurality of multi-stack nanosheet structures arranged on the substrate in a channel width direction,
• wherein the multi-stack nanosheet structures comprise at least one lower nanosheet stack and at least one upper nanosheet stack formed above the lower nanosheet stack,
• wherein the lower and upper nanosheet stacks comprise a plurality of nanosheet layers as current channels for a transistor structure, and
• wherein the lower nanosheet stacks of a 1st multi-stack nanosheet structure and a 2nd multi-stack nanosheet structure among the multi-stack nanosheet structures have different channel widths, corresponding to widths of the nanosheet layers, in a channel width direction.

A method of manufacturing a multi-stack semiconductor device, the method comprising operations of:

• (a) stacking at least one set of lower nanosheet layers and sacrificial layers, and at least one set of upper nanosheet layers and sacrificial layers in this order on a substrate;
• (b) patterning the set of upper nanosheet layers and sacrificial layers to obtain a plurality of upper nanosheet stacks;
• (c) conformally forming a 1st spacer layer on the upper nanosheet stacks;
• (d) selectively removing the 1st spacer layer formed on sidewalls of the upper nanosheet stacks such that the 1st spacer layer on both sidewalls of a 1st upper nanosheet stack and only one of two sidewalls of a 2nd upper nanosheet stack are removed;
• and
• (e) patterning the set of lower nanosheet layers and sacrificial layers using the remaining 1st spacer layer as mask to obtain a plurality of lower nanosheet stacks corresponding to the upper nanosheet stacks such that a width of a 2nd lower nanosheet stack patterned below the 2nd upper nanosheet stack is greater than a width of a 1st lower nanosheet stack patterned below the 1st upper nanosheet stack by a thickness of the 1st spacer layer.