Single-crystal transistors for memory devices

An apparatus, comprising:

• a deck of memory cells;
• a dielectric portion above the deck of memory cells;
• and
• a plurality of transistors coupled with the deck of memory cells, wherein each transistor of the plurality of transistors comprises:
• a semiconductor portion in contact with a top surface of the dielectric portion, the semiconductor portion comprising a single-grain crystalline arrangement and having a tapered extension into the dielectric portion;
• a first terminal in contact with a first portion of a top surface of the semiconductor portion;
• a second terminal in contact with a second portion of the top surface of the semiconductor portion;
• and
• a gate conductor operable to modulate a conductivity of the semiconductor portion between the first terminal and the second terminal.

A transistor formed by a process of:

• forming a cavity extending through at least a portion of one or more dielectric materials, wherein the cavity includes a taper from a first cross-sectional area toward a point;
• depositing a semiconductor material in the cavity and above the one or more dielectric materials;
• forming the semiconductor material in a single crystalline arrangement based at least in part on heating and cooling the semiconductor material;
• and
• forming a channel portion of the transistor based at least in part on doping the single crystalline arrangement of the semiconductor material.