Array substrate, method for fabricating same, and display panel

A method for fabricating an array substrate, comprising:

• defining an opening area and a non-opening area on a first substrate;
• forming an active layer disposed on the first substrate and located in the non-opening area;
• forming a gate insulating layer covering a side of the active layer away from the first substrate and located in the opening area and the non-opening area;
• forming a gate electrode layer disposed on a side of the gate insulating layer away from the first substrate and located in the non-opening area;
• forming a first interlayer insulating layer on a side of a part of the gate electrode layer and the gate insulating layer in the non-opening area away from the first substrate, wherein a projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening area on the first substrate;
• forming a second interlayer insulating layer located on a side of the first interlayer insulating layer in the non-opening area away from the first substrate and covering a part of the gate insulating layer in the opening area, wherein a surface of a part of the second interlayer insulating layer in the opening area close to the first substrate is attached to a surface of a part of the gate insulating layer in the opening area away from the first substrate;
• and
• forming a source/drain electrode layer disposed on a side of the second interlayer insulating layer away from the first substrate, located in the non-opening area, and electrically connected to the active layer through via holes going through the second interlayer insulating layer, the first interlayer insulating layer, and the gate insulating layer.

A display panel, comprising an array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, wherein the array substrate comprises an opening area and a non-opening area and further comprises:

• a first substrate;
• an active layer disposed on the first substrate and located in the non-opening area;
• a gate insulating layer covering a side of the active layer away from the first substrate and located in the opening area and the non-opening area;
• a gate electrode layer disposed on a side of the gate insulating layer away from the first substrate, and located in the non-opening area;
• and
• a first interlayer insulating layer disposed on a side of the gate electrode layer and the gate insulating layer away from the first substrate and located in the non-opening area;
• a second interlayer insulating layer disposed on a side of the first interlayer insulating layer away from the first substrate and located in the opening area and the non-opening area;
• and
• a source/drain electrode layer disposed on a side of the second interlayer insulating layer away from the first substrate, located in the non-opening area, and electrically connected to the active layer through via holes going through the second interlayer insulating layer, the first interlayer insulating layer, and the gate insulating layer;
• wherein a projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening area on the first substrate;
• a surface of a part of the second interlayer insulating layer in the opening area close to the first substrate is attached to a surface of a part of the gate insulating layer in the opening area away from the first substrate.