Interdigitated device stack

A semiconductor device, comprising:

• pairs of transistors stacked over a substrate, resulting in a vertical stack perpendicular to a working surface of the substrate, each pair of transistors including a respective top transistor that has a respective top gate and is stacked over a respective bottom transistor having a respective bottom gate, wherein
• a plurality of bottom gate structures extends from a central region of the vertical stack to a first side of the vertical stack,
• a plurality of top gate structures extends from the central region of the vertical stack to a second side of the vertical stack opposite the first side of the vertical stack,
• a first contact structure positioned on the first side of the vertical stack and positioned over a respective bottom gate structure of a topmost pair of transistors and bypasses a respective top gate structure of the topmost pair of transistors from the first side of the vertical stack;
• and
• a second contact structure positioned over the respective top gate structure of the topmost pair of transistors.

A semiconductor device, comprising:

• a first pair of transistors positioned over a substrate, the first pair of transistors including a first transistor that has a first gate structure and is positioned over the substrate and a second transistor that has a second gate structure and is stacked over the first transistor;
• a second pair of transistors stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate, the second pair of transistors including a third transistor that has a third gate structure and is stacked over the second transistor and a fourth transistor that has a fourth gate structure and is stacked over the third transistor;
• a first inter-level contact positioned on the first side of the vertical stack and configured to electrically connect the first gate structure to the third gate structure;
• and
• a second inter-level contact positioned on the second side of the vertical stack and configured to electrically connect the second gate structure to the fourth gate structure, wherein
• the third gate structure extends from a central region of the vertical stack to a first side of the vertical stack,
• the second gate structure and the fourth gate structure both extend from the central region of the vertical stack to a second side of the vertical stack opposite the first side of the vertical stack,
• the first inter-level contact is positioned between the first gate structure and the third gate structure, and
• the first inter-level contact bypasses the second gate structure from the first side of the vertical stack.