Electrostatic discharge protection circuit including a pulse detection circuit

An electrostatic discharge protection circuit, comprising:

• a pulse detection circuit, configured to detect an electrostatic pulse signal, the pulse detection circuit having a first end connected to a first voltage, a second end connected to a second voltage, and a third end configured to output a pulse detection signal;
• a delay circuit, configured to delay or enhance driving capability of the pulse detection signal, the delay circuit having a first end connected to the first voltage, a second end connected to the second voltage, a third end connected to the third end of the pulse detection circuit, a fourth end configured to output a first delay signal, and a fifth end configured to output a second delay signal;
• a control circuit, configured to generate a control signal based on the first delay signal and the second delay signal, the control circuit having a first end connected to the first voltage, a second end connected to the second voltage, a third end connected to the fifth end of the delay circuit, a fourth end connected to the fourth end of the delay circuit, and a fifth end configured to output the control signal;
• and
• a discharge circuit, configured to open or close an electrostatic charge discharge passage based on the control signal, the discharge circuit having a first end connected to the first voltage, a second end connected to the second voltage, and a third end connected to the fifth end of the control circuit;
• wherein the delay circuit comprises:
• a first inverter having a first end used as the third end of the delay circuit, a second end connected to the first voltage, a third end connected to the second voltage, and a fourth end used as the fourth end of the delay circuit;
• and
• a second inverter having a first end connected to the fourth end of the first inverter, a second end connected to the first voltage, a third end connected to the second voltage, and a fourth end used as the fifth end of the delay circuit;
• wherein the control circuit comprises:
• a third PMOS transistor, a source of the third PMOS transistor being connected to the first voltage;
• a third NMOS transistor, a gate of the third NMOS transistor being connected to the fourth end of the first inverter, a drain of the third NMOS transistor being connected to a drain of the third PMOS transistor, and a source of the third NMOS transistor being connected to the second voltage;
• a fourth PMOS transistor, a gate of the fourth PMOS transistor being connected to the drain of the third PMOS transistor and the drain of the third NMOS transistor, and a source of the fourth PMOS transistor being connected to the first voltage;
• and
• a fourth NMOS transistor, a gate of the fourth NMOS transistor being connected to the fourth end of the second inverter, a drain of the fourth NMOS transistor being connected to a drain of the fourth PMOS transistor and a gate of the third PMOS transistor and used as the fifth end of the control circuit.