TSV check circuit with replica path
AssigneeMicron Technology, Inc.
InventorHarutaka Makabe
Life of this patent
Estimating the term…
Abstract
Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.
Claims20
A method comprising:
- charging a first path and a second path with a first voltage;
- comparing potentials of the first path and the second path after charging;
- activating, responsive to the potential of the first path being lower than the potential of the second path, an output signal at a low level;
- and
- replacing the first path with the second path responsive to the output signal being at the low level.
A method comprising:
- charging a first path and a second path with a first voltage;
- comparing potentials of the first path and the second path after charging;
- activating, responsive to the potential of the first path being lower than the potential of the second path, an output signal at a low level;
- replacing the first path with the second path;
- and
- charging the first and second paths simultaneously with the first voltage.
An apparatus comprising:
- a first signal path including a first TSV;
- a first node coupled to the first signal path;
- a second signal path including a second TSV;
- a second node coupled to the second signal path;
- and
- a comparator configured to compare a level at the first node coupled to the first signal path and a level at the second node coupled to the second signal path in response to a comparison signal.
An apparatus comprising:
- a first signal path including a first TSV;
- a first node coupled to the first signal path;
- a second signal path including a second TSV;
- a second node coupled to the second signal path;
- and
- a comparator configured to compare a level at the first node and a level at the second node with each other in response to a comparison signal, wherein the comparator is configured to place an output signal at a low level responsive to the level at the first node being lower than the level at the second node, wherein a fail signal is activated, and wherein the first signal path is replaced with the second signal path responsive to the activation of the fail signal.
An apparatus comprising:
- a first signal path including a first TSV;
- a first node coupled to the first signal path;
- a second signal path including a second TSV;
- a second node coupled to the second signal path;
- and
- a comparator configured to compare a level at the first node and a level at the second node with each other in response to a comparison signal, wherein the first signal path includes a first parasitic capacitance and the second signal path includes a second parasitic capacitance, wherein the first parasitic capacitance and the second capacitance have the same value.
An apparatus comprising:
- a first signal path including a first TSV and a first transistor, the first transistor configured to receive a selection signal;
- a first node coupled to the first signal path;
- a second signal path including a second TSV and a second transistor, the second transistor configured to receive an enable signal;
- a second node coupled to the second signal path;
- and
- a comparator configured to:
- compare a level at the first node and a level at the second node with each other;
- place an output signal at a low level if the level at the second node is higher than the level at the first node;
- and
- activate a fail signal in response to the output signal being at the low level.
Dependencies are inferred from the claim text.