Semiconductor package including a dualized signal wiring structure

A semiconductor package comprising:

• a substrate;
• a first package comprising a plurality of lower pads, plurality of upper pads formed on an upper external surface of the first package, and a first semiconductor chip including a first chip pad and configured to transmit or receive a pre-defined signal through the first chip pad, and mounted on the substrate;
• and
• a second package comprising a second semiconductor chip controlled by the first semiconductor chip and configured to transmit or receive a pre-defined signal through a second chip pad of the second semiconductor chip, and mounted on the first package or the substrate,
• wherein the first package comprises:
• a first wiring structure connecting the first chip pad to a first lower pad among the plurality of lower pads;
• a plurality of second wiring structures connecting a plurality of second lower pads among the plurality of lower pads to the upper pad, the plurality of second wiring structures respectively including a plurality of conductive connectors that face side surfaces of the semiconductor chip,
• a first external connection terminal connected to the first lower pad;
• and
• a plurality of second external connection terminals respectively connected to the plurality of second lower pads,
• wherein, when the first package and the second package are horizontally mounted on the substrate, the first wiring structure and the plurality of second wiring structures are electrically separated, the first external connection terminal is connected to a wiring structure formed in the substrate, the wiring structure transmit or receive the pre-defined signal between the first semiconductor chip and the second semiconductor chip, the plurality of second external connection terminals are electrically separated to the wiring structure the first semiconductor chip is laterally disposed between the plurality of conductive connectors, and none of the plurality of conductive connectors are electrically connected to the first semiconductor chip.

A semiconductor package comprising:

• a plurality of lower pads;
• a plurality of upper pads;
• a semiconductor chip including a chip pad and configured to transmit a first signal through the chip pad to a memory chip included in a memory package or receive the first signal through the chip pad from the memory chip included in the memory package;
• a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads;
• and
• a plurality of second wiring structures respectively connecting a plurality of second lower pads among the plurality of lower pads to the plurality of upper pads, the plurality of second wiring structures respectively including a plurality of conductive connectors that face side surfaces of the semiconductor chip,
• a first external connection terminal connected to the first lower pad;
• and
• a plurality of second external connection terminals respectively connected to the plurality of second lower pads,
• wherein the first lower pad and one of the plurality of second lower pads are physically separated from each other in the semiconductor package, and the first wiring structure and the plurality of second wiring structures are physically separated from each other in the semiconductor package,
• wherein the semiconductor chip comprises a universal flash storage (UFS) controller configured to exchange the first signal through the chip pad,
• wherein when the semiconductor package and the memory package are horizontally mounted on a substrate base, the first wiring structure and the plurality of second wiring structures are electrically separated, the first external connection terminal is connected to a wiring structure formed in the substrate base, the plurality of second external connection terminals are electrically separated to the wiring structure, the semiconductor chip is laterally disposed between the plurality of conductive connectors, and none of the plurality of conductive connectors are electrically connected to the semiconductor chip.