Clamped semiconductor wafers and semiconductor devices
AssigneeSanDisk Technologies LLC
InventorsKirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
Life of this patent
Estimating the term…
Abstract
Clamped semiconductor wafers and clamped semiconductor devices include reservoirs filled with a flowable metal which hardens to allow the wafers/devices to be shipped or stored. The hardened metal may also be reflowed to a liquid to allow clamping of the semiconductor wafers together and to allow clamping of the semiconductor packages together. The flowable metal may be filled into the reservoirs as a liquid or paste. Thereafter, the flowable metal may be cooled to harden the flowable metal into a clamping member.
Claims19
A semiconductor wafer, comprising:
- first and second opposed major surfaces, the first surface defining a first direction parallel to the first surface, and a second direction between the first and second opposed major surfaces;
- a dielectric layer adjacent the first major surface;
- integrated circuits formed in the dielectric layer;
- bond pads in the first major surface, the bond pads electrically coupled to the integrated circuits;
- and
- a set of one or more reservoirs formed in the dielectric layer and open at the first major surface, the set of one or more reservoirs configured to receive a flowable metal to clamp the semiconductor wafer to a second semiconductor wafer upon hardening of the flowable metal in the set of one or more reservoirs, a reservoir of the set of one or more reservoirs comprising:
- a first section having a first sub-section extending in the first direction, and a second sub-section extending in the second direction, and
- a second section having a third sub-section extending in the first direction and a fourth sub-section extending in the second direction,
- wherein the first and second sections are connected to each other through one or more additional sections formed in the second semiconductor wafer.
A semiconductor die, comprising:
- first and second opposed major surfaces;
- a dielectric layer adjacent the first major surface;
- integrated circuits formed in the dielectric layer;
- bond pads in the first major surface, the bond pads electrically coupled to the integrated circuits;
- and
- a set of one or more reservoirs formed in the dielectric layer and open at the first major surface, the set of one or more reservoirs configured to receive a flowable metal to clamp the semiconductor die to a second semiconductor die upon hardening of the flowable metal in the set of one or more reservoirs, a reservoir of the set of one or more reservoirs comprising:
- a first “T”-shaped section having a first sub-section extending in a first direction, and a second sub-section extending in a second direction orthogonal to the first direction, and
- a second section having a third sub-section extending in the first direction and a fourth sub-section extending in the second direction,
- wherein the first and second sections are connected to each other through one or more additional sections formed in the second semiconductor wafer.
A semiconductor device, comprising:
- a signal carrier medium comprising first and second opposed major surfaces, the first surface defining a first direction parallel to the first surface, and a second direction between the first and second opposed major surfaces;
- and
- a set of one or more reservoirs formed in the signal carrier medium and open to at one of the first and second major surfaces, the set of one or more reservoirs configured to receive a flowable metal to clamp the semiconductor device to a second semiconductor device upon hardening of the flowable metal in the set of one or more reservoirs, a reservoir of the set of one or more reservoirs comprising:
- a first section having a first sub-section extending in the first direction, and a second sub-section extending in the second direction, and
- a second section having a third sub-section extending in the first direction and a fourth sub-section extending in the second direction,
- wherein the first and second sections are connected to each other through one or more additional sections formed in the second semiconductor wafer.
Dependencies are inferred from the claim text.