Semiconductor chip and semiconductor package including the same

A semiconductor chip comprising:

• a semiconductor substrate having a first surface and a second surface opposite to the first surface, and an active layer disposed in a portion of the semiconductor substrate that is adjacent to the first surface;
• a through electrode extending in the semiconductor substrate in a vertical direction, the through electrode having a lower surface extending partially through the semiconductor substrate and directly connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate;
• a chip pad disposed on the first surface of the semiconductor substrate and connected to the active layer;
• a passivation layer disposed on the second surface of the semiconductor substrate;
• a bonding pad arranged on a portion of the passivation layer and the upper surface of the through electrode, the bonding pad having a cross-section with a “T” shape in the vertical direction, the bonding pad is connected to the through electrode;
• and
• a pad seed layer disposed on a lower portion of the bonding pad.

A semiconductor package comprising:

• a package substrate;
• a lower semiconductor chip mounted on the package substrate, wherein the lower semiconductor chip comprises:
• a lower semiconductor substrate having a first surface and a second surface opposite to the first surface and having a lower active layer at a portion of the lower semiconductor substrate adjacent to the first surface thereof;
• a lower through electrode extending in the lower semiconductor substrate in a vertical direction, the lower through electrode having a lower surface extending partially through the lower semiconductor substrate and directly connected to the lower active layer and an upper surface positioned at a level lower than a level of the second surface of the lower semiconductor substrate;
• a lower passivation layer disposed on the second surface of the lower semiconductor substrate;
• a lower bonding pad arranged on a portion of the lower passivation layer and the upper surface of the lower through electrode, the lower bonding pad having a cross-section with a “T” shape in the vertical direction, the lower bonding pad is connected to the lower through electrode;
• and a lower pad seed layer arranged on a lower portion of the lower bonding pad;
• an upper semiconductor chip mounted on the lower semiconductor chip, wherein the upper semiconductor chip comprises:
• an upper semiconductor substrate having a third surface facing the lower semiconductor chip and a fourth surface opposite to the third surface and having an upper active layer at a portion of the upper semiconductor chip adjacent to the third surface thereof;
• an upper chip pad disposed on the third surface of the upper semiconductor substrate and connected to the upper active layer;
• and an upper chip connection terminal disposed between the upper chip pad and the lower bonding pad;
• and
• a molding layer surrounding the lower semiconductor chip and the upper semiconductor chip on the package substrate.