Wafer structure and semiconductor device

A semiconductor device, comprising:

• a semiconductor substrate that has a chip region and a dummy region that surrounds the chip region, in a plan view;
• a first dielectric layer on a first surface of the semiconductor substrate;
• a second dielectric layer on the first dielectric layer;
• a dielectric pattern between the first dielectric layer and the second dielectric layer;
• a through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate;
• and
• a conductive pad in the second dielectric layer and on the through via,
• wherein the dielectric pattern is spaced apart from a sidewall of the through via, and
• wherein the dielectric pattern includes:
• an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad;
• and
• a dummy dielectric pattern on the dummy region of the semiconductor substrate.

A wafer structure, comprising:

• a semiconductor substrate that includes a chip region and a scribe lane region and having a first surface and a second surface;
• a plurality of integrated circuits on the second surface at the chip region of the semiconductor substrate;
• a circuit layer on the second surface of the semiconductor substrate, the circuit layer including a dielectric layer and a wiring structure, the wiring structure being in the dielectric layer and coupled to the integrated circuits;
• a lower conductive pad on a bottom surface of the circuit layer and coupled to the wiring structure;
• a first dielectric layer on the first surface at the chip region and the scribe lane region of the semiconductor substrate;
• a second dielectric layer on the first dielectric layer;
• a dielectric pattern between the first dielectric layer and the second dielectric layer;
• a through via that penetrates the first dielectric layer and the chip region of the semiconductor substrate;
• and
• a conductive pad in the second dielectric layer and on the through via, the conductive pad being coupled to the through via,
• wherein the through via includes a barrier pattern and a conductive via,
• wherein the barrier pattern is between the semiconductor substrate and the conductive via,
• wherein the conductive pad includes a barrier pad and a metal pad on the barrier pad,
• wherein the dielectric pattern includes a material different from a material of the first dielectric layer and a material different from the second dielectric layer, and
• wherein the dielectric pattern includes:
• an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad;
• and
• an alignment key pattern on the scribe lane region of the semiconductor substrate.