Semiconductor memory device having word lines surrounded by memory layers and method of making the semiconductor memory device

A semiconductor memory device comprising:

• a semiconductor structure;
• a plurality of dielectric segments and a plurality of conductive segments that are alternatingly stacked over the semiconductor structure in a first direction perpendicular to the semiconductor structure and that extend in a second direction perpendicular to the first direction;
• a plurality of channel segments that extend through the dielectric segments and the conductive segments in the first direction;
• a plurality of conductive lines that extend in the first direction, each of the channel segments surrounding corresponding two of the conductive lines;
• a plurality of memory segments, each of the memory segments surrounding the channel segments, and surrounding a respective one of the conductive segments;
• and
• a plurality of staircase vias that respectively penetrate the memory segments and that are respectively and electrically connected to the conductive segments.

A semiconductor memory device comprising:

• a semiconductor structure;
• a plurality of dielectric segments and a plurality of conductive segments that are alternatingly stacked over the semiconductor structure in a first direction perpendicular to the semiconductor structure and that extend in a second direction perpendicular to the first direction;
• a plurality of channel segments that extend through the dielectric segments and the conductive segments in the first direction;
• a plurality of conductive lines that extend in the first direction, each of the channel segments surrounding corresponding two of the conductive lines;
• a plurality of isolation segments that extend in the first direction, each of the isolation segments being disposed between corresponding two of the conductive lines and being surrounded by a corresponding one of the channel segments;
• a plurality of memory segments, each of the memory segments surrounding the channel segments, and surrounding a respective one of the conductive segments;
• and
• a plurality of staircase vias that respectively penetrate the memory segments and that are respectively and electrically connected to the conductive segments.