Semiconductor memory device

A semiconductor memory device comprising:

• a first conductive layer;
• a stacked body including a plurality of second conductive layers and a plurality of first insulating layers alternately stacked one by one above the first conductive layer, and including a stepped portion in which the plurality of second conductive layers is terraced;
• a plurality of first pillars arranged in a memory region that is away from the stepped portion in a first direction that crosses a stacking direction of the stacked body, each first pillar including a semiconductor layer that penetrates the stacked body and connects with the first conductive layer, and forming a memory cell at an intersection with at least a part of the plurality of second conductive layers;
• and
• a plate-like portion that extends in the stacked body from the stepped portion to the memory region continuously in the stacking direction and in the first direction, and divides the stacked body in a second direction that crosses both the stacking direction and the first direction, wherein
• the plate-like portion includes:
• a sidewall insulating layer covering sidewalls that are opposed each other in the second direction of the plate-like portion;
• and
• a third conductive layer that extends inside the sidewall insulating layer from the stepped portion to the memory region continuously, and is electrically connected to the first conductive layer, and
• the sidewall insulating layer includes, in the stepped portion intermittently in the first direction, first portions each having a thickness larger than a thickness of a second portion other than the first portions in a direction that crosses the stacking direction.