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US 12,224,238 B2Granted
MIM eFuse memory devices and memory array
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng Chang, Chia-En Huang
Life of this patent
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Abstract
A memory device is disclosed. The memory device includes a transistor and a resistor electrically connected to the transistor. The transistor and the resistor form a first one-time programmable (OTP) memory cell. The resistor includes a metal-based layer with a resistivity configured to irreversibly transition from a first resistance state to a second resistance state.
Claims19
A memory device, comprising:
- a transistor;
- and
- a resistor electrically connected to the transistor, the transistor and the resistor forming a first one-time programmable (OTP) memory cell,
- wherein the resistor includes a metal-based layer with a resistivity configured to irreversibly transition from a first resistance state to a second resistance state, and
- wherein the metal-based layer has a first surface and a second surface, the first surface in direct contact with a via structure that is disposed between adjacent ones of a plurality of metallization layers, the second surface in direct contact with an interconnect structure that is disposed in one of the plurality of metallization layers, the first surface and the second surface being opposite to each other.
2 more elements
A memory array, comprising:
- a substrate;
- and
- a memory array disposed over the substrate and comprising a plurality of one-time programmable (OTP) memory cells, each of the OTP memory cells comprising a transistor and a resistor electrically connected to each other,
- wherein the resistor of each of the OTP memory cells is formed of a metal-based material configured to present a low resistance state prior to programming the corresponding memory cell and a high resistance state in response to programming the corresponding memory cell, and
- wherein the resistor has a first surface and a second surface, the first surface in direct contact with a via structure that is disposed between adjacent ones of a plurality of metallization layers, the second surface in direct contact with an interconnect structure that is disposed in one of the plurality of metallization layers, the first surface and the second surface being opposite to each other.
2 more elements
A memory device, comprising:
- a transistor;
- and
- a resistor electrically connected to the transistor, the transistor and the resistor forming a one-time programmable (OTP) memory cell,
- wherein the resistor includes a metal-based layer including a material allowing a resistivity of the resistor to irreversibly transition from a first resistance state to a second resistance state,
- wherein the metal-based layer has a first surface and a second surface, the first surface in direct contact with a via structure that is disposed between adjacent ones of a plurality of metallization layers, the second surface in direct contact an interconnect structure that is disposed in one of the plurality of metallization layers, the first surface and the second surface being opposite to each other.
2 more elements
Dependencies are inferred from the claim text.