Method of manufacturing a via and a metal wiring for a semiconductor device

A method of manufacturing a semiconductor device comprising a lower wiring pattern, an upper wiring pattern and a pair of vias connecting the lower wiring pattern and the upper wiring pattern, the method comprising:

• forming a conductive layer over a substrate;
• forming a dielectric layer over the conductive layer;
• forming the pair of vias in the dielectric layer;
• forming a hard mask pattern over the dielectric layer;
• forming an opening in the dielectric layer between the pair of vias;
• extending the opening through the conductive layer to form the lower wiring pattern;
• forming a second dielectric layer filling the opening;
• and
• forming the upper wiring pattern over the pair of vias and the second dielectric layer.

A method of manufacturing a semiconductor device comprising:

• forming a first interlayer dielectric (ILD) layer over a substrate;
• forming a first conductive layer over the first interlayer dielectric (ILD) layer;
• forming a second ILD layer over the first conductive layer;
• forming a first via and a second via in the second ILD layer contacting an upper surface of the first conductive layer;
• forming an opening in the second ILD layer between the first via and the second via,
• wherein the opening is bounded by sidewalls of the first via and the second via;
• extending the opening into the first conductive layer exposing a portion of the first ILD layer, thereby patterning the first conductive layer into a first patterned conductive layer and a second patterned conductive layer;
• and
• forming a third ILD layer between the first patterned conductive layer and the second patterned conductive layer and between the first via and the second via.