Address signal transmission circuit, address signal transmission method and storage system

A storage system, comprising an address signal transmission circuit, wherein the address signal transmission circuit comprises:

• a transmission control circuit, connected to an address bus, configured to receive address signals from the address bus, acquire a first address signal and a second address signal, and generate and output an inversion flag signal based on the first address signal and the second address signal, wherein the first address signal is an address signal received in a previous time and the second address signal is a currently received address signal;
• and
• a selection circuit, connected to the address bus, configured to receive the address signals from the address bus, determine, in response to the inversion flag signal, whether the second address signal is to be inverted, and correspondingly output one of the second address signal or an address inverted signal, wherein the selection circuit inverts the second address signal to obtain the address inverted signal;
• wherein the transmission control circuit is further configured to acquire a number of changed bits of address data in the first address signal and the second address signal and generate the inversion flag signal based on a relation between the number of changed bits and a predetermined value, wherein the number of changed bits of the address data is N, and the predetermined value satisfies M=N/2+1, M being the predetermined value and N being a positive integer;
• and
• the selection circuit is further configured to, in a case where the number of changed bits is greater than or equal to the predetermined value, invert the second address signal to obtain the address inverted signal and output the address inverted signal, and in a case where the number of changed bits is smaller than the predetermined value, directly output the second address signal;
• wherein the transmission control circuit comprises:
• a latch sub-circuit, connected to the address bus, and configured to latch and output a received address signal;
• and
• a comparison and determination sub-circuit, connected to the address bus and configured to acquire the second address signal, connected to the latch sub-circuit and configured to acquire the first address signal latched in the previous time, wherein the comparison and determination sub-circuit is configured to acquire the number of changed bits according to the first address signal and the second address signal, and compare the number of changed bits with the predetermined value to generate the inversion flag signal.

An address signal transmission circuit, comprising:

• a transmission control circuit, connected to an address bus, configured to receive address signals from the address bus, acquire a first address signal and a second address signal, and generate and output an inversion flag signal based on the first address signal and the second address signal, wherein the first address signal is an address signal received in a previous time and the second address signal is a currently received address signal;
• and
• a selection circuit, connected to the address bus, configured to receive the address signals from the address bus, determine, in response to the inversion flag signal, whether the second address signal is to be inverted, and correspondingly output one of the second address signal or an address inverted signal, wherein the selection circuit inverts the second address signal to obtain the address inverted signal;
• a delay circuit, the delay circuit being connected between the selection circuit and the address bus, and configured to control the time when the second address signal is transmitted to the selection circuit, such that the selection circuit, prior to receiving the second address signal, receives the inversion flag signal.

An address signal transmission circuit, comprising:

• a transmission control circuit, connected to an address bus, configured to receive address signals from the address bus, acquire a first address signal and a second address signal, and generate and output an inversion flag signal based on the first address signal and the second address signal, wherein the first address signal is an address signal received in a previous time and the second address signal is a currently received address signal;
• and
• a selection circuit, connected to the address bus, configured to receive the address signals from the address bus, determine, in response to the inversion flag signal, whether the second address signal is to be inverted, and correspondingly output one of the second address signal or an address inverted signal, wherein the selection circuit inverts the second address signal to obtain the address inverted signal;
• an address receiving circuit, wherein the address receiving circuit is configured to receive the second address signal or the address inverted signal outputted by the selection circuit, and in response to the inversion flag signal, output a target address signal, wherein the target address signal is the same as the second address signal received by the selection circuit;
• wherein the selection circuit is configured to, in response to a first enable control signal, receive the second address signal, and the address receiving circuit is configured to, in response to a second enable control signal, receive the second address signal;
• or,
• wherein the address signal transmission circuit further comprises:
• an address decoding circuit, connected to the output end of the address receiving circuit, and configured to perform address decoding processing on the target address signal;
• or,
• an address signal transmission sub-circuit, connected between the selection circuit and the address receiving circuit, and configured to transmit the second address signal or the address inverted signal;
• and an identifier signal transmission circuit, connected between the transmission control circuit and the address receiving circuit, and configured to transmit the address inverted signal.

An address signal transmission circuit, comprising:

• a transmission control circuit, connected to an address bus, configured to receive address signals from the address bus, acquire a first address signal and a second address signal, and generate and output an inversion flag signal based on the first address signal and the second address signal, wherein the first address signal is an address signal received in a previous time and the second address signal is a currently received address signal;
• and
• a selection circuit, connected to the address bus, configured to receive the address signals from the address bus, determine, in response to the inversion flag signal, whether the second address signal is to be inverted, and correspondingly output one of the second address signal or an address inverted signal, wherein the selection circuit inverts the second address signal to obtain the address inverted signal;
• an address receiving circuit, wherein the address receiving circuit is configured to receive the second address signal or the address inverted signal outputted by the selection circuit, and in response to the inversion flag signal, output a target address signal, wherein the target address signal is the same as the second address signal received by the selection circuit;
• wherein the address receiving circuit comprises N address receiving sub-circuits, each of the address receiving sub-circuits being configured to receive the single-bit address data in the second address signal or the single-bit address inverted data in the address inverted signal, and each of the address receiving sub-circuits being configured to, in response to the inversion flag signal, determine whether the corresponding single-bit address data in the received second address signal or the address inverted signal is to be inverted.