Apparatuses and methods of memory access control with section predecoding and section selection

An apparatus comprising:

• a plurality of memory cell matrices including memory cells;
• a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices;
• a section predecoder configured to decode a portion of row address signals and further configured to activate a section signal among a plurality of corresponding section signals responsive to the portion of row address signals;
• a section selection control circuit configured to provide a plurality of sets of section sub signals based on the plurality of section signals, the plurality of sets of section sub signals including:
• a set of first section sub signals including an active first section sub signal;
• and
• a set of second section sub signals including an active second section sub signal;
• and
• a plurality of section selection circuits corresponding to the plurality of sections,
• wherein one section selection circuit among the plurality of section selection circuits is configured to activate the corresponding section responsive to the active first and second section sub signals,
• wherein:
• the plurality of memory cell matrices comprises a first memory cell matrix at an end;
• the plurality of memory cell matrices comprises a second memory cell matrix;
• and
• a number of word lines coupled to the second memory cell matrix is equal to or greater than twice a number of word lines coupled to the first memory cell matrix.