High speed memory device with data masking

A method for masking data, comprising:

• forming a first deserializer and a second deserializer of a same circuit structure;
• converting serial data using the first deserializer to output parallel data based on a set of write clock signals, the parallel data having a first timing alignment with regard to the set of write clock signals;
• outputting a mask pattern using the second deserializer based on the set of write clock signals, the mask pattern having a second timing alignment with regard to the set of write clock signals;
• and
• combining the parallel data with the mask pattern to generate valid data,
• wherein the first deserializer outputs the parallel data and the second deserializer outputs the mask pattern at a same time, and
• wherein the same circuit structure includes:
• a sampling stage configured to sample a data input carrying the serial data based on a data strobe signal;
• a first shift stage including a cascaded shift register path configured to shift the sampled serial data based on a first write clock signal and generate intermediate parallel data;
• a second shift stage including parallel cascaded shift register paths to shift the intermediate parallel data based on a second write clock signal and generate the parallel data;
• and
• an output stage configured to output the parallel data based on a third write clock signal.

A memory device, comprising:

• a memory cell array configured to write data in parallel;
• and
• peripheral circuitry comprising:
• a first deserializer configured to convert serial data to parallel data with a first timing alignment with regard to a set of write clock signals;
• a second deserializer configured to generate a mask pattern with a second timing alignment with regard to the set of write clock signals;
• and
• a write data converter coupled to the first deserializer and the second deserializer, the write data converter configured to generate valid data for writing to the memory cell array by combining the parallel data with the mask pattern,
• wherein the first deserializer outputs the parallel data and the second deserializer outputs the mask pattern at a same time, and the first deserializer and the second deserializer are configured to have a same circuit structure that includes:
• a sampling stage configured to sample a data input carrying the serial data based on a data strobe signal;
• a first shift stage including a cascaded shift register path configured to shift the sampled serial data based on a first write clock signal and generate intermediate parallel data;
• a second shift stage including parallel cascaded shift register paths to shift the intermediate parallel data based on a second write clock signal and generate the parallel data;
• and
• an output stage configured to output the parallel data based on a third write clock signal.