Memory system

A memory system comprising:

• a plurality of first wirings extending in a first direction;
• a plurality of second wirings extending in a second direction intersecting the first direction;
• a memory cell connected to the first wiring and the second wiring between the first wiring and the second wiring at a position where the first wiring and the second wiring intersect as viewed from a third direction perpendicular with respect to a plane including the first direction and the second direction;
• a third wiring connectable to each of the plurality of first wirings;
• a sense amplifier connected to the third wiring, the sense amplifier being configured to execute a read operation to the memory cell;
• a first switching element between the plurality of first wirings and the third wiring;
• a first transistor including a first terminal, a second terminal, and a gate terminal, the first terminal being connected to a first node on a wiring connecting the first wiring and the third wiring, the second terminal being connected to a first power source line, and the gate terminal being connected to a second node on a wiring connecting the first wiring and the third wiring;
• and
• a control circuit,
• wherein:
• the first node is positioned further to the side of the sense amplifier than the first switching element,
• the second node is positioned further to the side of the memory cell than the first switching element, and
• the control circuit is configured to:
• connect the first node and the second node when the first switching element is in an ON state, and
• connect the second node and the gate terminal of the first transistor when the first switching element is in an OFF state.