US 12,224,030 B2Granted

Memory system

AssigneeWindbond Electronics Corp.

InventorTakahiko Sato

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Abstract

The present invention provides a memory system in which a semiconductor memory device can be accessed properly. The memory system includes a memory controller and a semiconductor memory device. The memory controller sends a command, an address, and first checking data to the semiconductor memory device. When the semiconductor memory device receives first response information that indicates that no error has been detected, it sends or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the command, the address, and the first checking data, it uses the first checking data to detect errors in the command and the address, and sends the first reply information when no error is detected, and when no error is detected in the command and the address, it sends or receives read data or write data from the semiconductor memory device.

Claims20

Dependent claims

A memory system, comprising:

a memory controller;
and
a semiconductor memory device;
wherein the memory controller is configured to:
send a command, an address and first check data for error detection of the command and the address to the semiconductor memory device;
and
when receiving first response information indicating that no error has been detected in the command and the address from the semiconductor memory device, based on the command, send to or receive from the semiconductor memory device of data to be read from or written into the address;
wherein the semiconductor memory device is configured to:
when receiving the command, the address and the first check data from the memory controller, use the first check data to perform error detection of the command and the address, and send the first response information to the memory controller when no error is detected in the command and the address;
and
when no error is detected in the command and the address, based on the command, send to or receive from the memory controller of the data to be read from or written into the address;
wherein the memory controller or the semiconductor memory device is configured to:
send the data to be read or write and second check data for error detection of the data to the other of the memory controller or the semiconductor memory device;
and
the other of the memory controller or the semiconductor memory device is configured to:
when receiving the data and the second check data, use the second check data to perform error detection of the data, and send third response information indicating that no error has been detected in the data to the memory controller and the semiconductor memory device.

13 more elements

A memory system, comprising:

a memory controller;
a semiconductor memory device;
wherein the memory controller is configured to:
send a command, an address and first check data for error detection of the command and the address to the semiconductor memory device;
and
when receiving first response information indicating that no error has been detected in the command and the address from the semiconductor memory device, based on the command, send to or receive from the semiconductor memory device of data to be read from or written into the address;
wherein the semiconductor memory device is configured to:
when receiving the command, the address and the first check data from the memory controller, use the first check data to perform error detection of the command and the address, and send the first response information to the memory controller when no error is detected in the command and the address;
and
when no error is detected in the command and the address, based on the command, send to or receive from the memory controller of the data to be read from or written into the address;
a request control part, generating a transform signal upon receiving a request for writing to or reading from the semiconductor memory device from a host device, wherein the transform signal transforms a transmitting mode of an address data signal sending and receiving between the memory controller and the semiconductor memory device;
and
a first serial control part, transforming the transmitting mode of the address data signal based on the transform signal.

10 more elements

A memory system, comprising:

a memory controller;
and
a semiconductor memory device;
wherein the memory controller is configured to:
send a command, an address and first check data for error detection of the command and the address to the semiconductor memory device;
and
when receiving first response information indicating that no error has been detected in the command and the address from the semiconductor memory device, based on the command, send to or receive from the semiconductor memory device of data to be read from or written into the address;
wherein the semiconductor memory device is configured to:
when receiving the command, the address and the first check data from the memory controller, use the first check data to perform error detection of the command and the address, and send the first response information to the memory controller when no error is detected in the command and the address;
and
when no error is detected in the command and the address, based on the command, send to or receive from the memory controller of the data to be read from or written into the address;
wherein when the semiconductor memory device is configured to generate an update request signal internally for executing an update, the semiconductor memory device is configured to:
in the duration between the generation of the update request signal and the execution of the update,
upon an error being detected in the command, the address, or the data received from the memory controller,
stop the execution of the update by re-sending the command, the address, or the data from the memory controller until no error is detected.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/987,435Filed 15 Nov 2022
Priority: JP 2021-20473617 Dec 2021
Published: US 2023/0197184 A122 Jun 2023
Granted: 11 Feb 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 29/52
Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation: protection of memory contents;…
G11C 7/1063
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: control signal…
G11C 7/109
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: control signal input…
G11C 11/4093
Read-write [R-W] circuits: input/output [I/O] data interface arrangements, e.g. data buffers

Family

US 2023/0197184 A1Pre-grant publication · published 22 Jun 2023
US 12,224,030 B2This patent

From the US filing history. Foreign family members aren’t listed.

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