US 12,224,028 B2 · Semiconductor chip and sequence checking circuit

Abstract

A semiconductor chip includes a physical layer and a processing circuit. The physical layer includes at least one sequence checking circuit and at least one signal transmission path, wherein the at least one sequence checking circuit is configured to generate at least one test result signal according to a clock signal and at least one test data signal transmitted through the at least one signal transmission path, and the clock signal is not transmitted through the at least one signal transmission path. The processing circuit is electrically coupled to the physical layer and is configured to determine an operation status of the at least one signal transmission path according to the voltage level of the at least one test result signal.

Claims20

Dependent claims

A semiconductor chip, including:

a physical layer, including at least one sequence checking circuit and at least one signal transmission path, wherein the at least one sequence checking circuit is configured to generate at least one test result signal according to a clock signal and at least one test data signal transmitted through the at least one signal transmission path, and the clock signal is not transmitted through the at least one signal transmission path;
and
a processing circuit, electrically coupled to the physical layer and configured to determine an operation status of the at least one signal transmission path according to the voltage level of the at least one test result signal.

A sequence checking circuit, configured to check a test data signal transmitted through a signal transmission path of a physical layer, comprises:

a first shift register circuit, configured to perform a first checking to a data sequence of the test data signal according to a plurality of rising edges of a clock signal, so as to output a first checking result signal;
a second shift register circuit, configured to perform a second checking to the data sequence of the test data signal according to a plurality of falling edges of the clock signal, so as to output a second checking result signal;
and
an output terminal logic gate, configured to output a test result signal according to the voltage level of the first checking result signal and the voltage level of the second checking result signal, wherein the test result signal is configured to indicate an operation status of the signal transmission path,
wherein the clock signal is not transmitted through the signal transmission path.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor chip and sequence checking circuit

Life of this patent

Semiconductor chip and sequence checking circuit

Life of this patent

Abstract

Claims20