Memory device with leakage current verifying circuit for minimizing leakage current

A memory device comprising:

• a memory array comprising a group of memory cells which comprises M word lines (WLs) and N bit lines as M and N are integers greater than 1;
• a leakage current verifying circuit for verifying leakage currents of the memory array;
• and
• a controller coupled to the memory array and the leakage current verifying circuit and configured at least to:
• initiate a program operation for a first column of memory cells which belongs to the group of memory cells and is connected to a first WL of the M WLs;
• set a verify condition which comprises a leakage current threshold during a leakage current verifying operation;
• perform, via the leakage current verifying circuit, a leakage current verifying operation for the first column of the memory cells by applying a negative voltage sweep to each of first remaining M−1 unselected WLs of the M WLs until finding a first negative voltage resulting in the first column of the memory cells having passed leakage current threshold;
• apply the program operation for the first column of the memory cells by applying the first negative voltage to each of the first remaining M−1 unselected WLs of the M WLs and a positive bit line voltage for the N BLs;
• determine whether a first address corresponding to the first column of the memory cells is a final address;
• initiate the program operation for a second column of memory cells which belongs to the group of memory cells and is connected to a second WL of the M WLs in response to the first address not being the final address;
• select the second WL of the M WLs corresponding to the second column of the memory cells;
• apply another negative voltage sweep to each of a second remaining M−1 unselected WLs of the M WLs until finding a second negative voltage resulting in the second column of the memory cells passing the leakage current threshold, wherein the first negative voltage is different from the second negative voltage;
• apply the program operation for the second column of the memory cells while applying the second negative voltage to each of the second remaining M−1 unselected WLs of the M WLs;
• apply a negative voltage for the first remaining M−1 unselected WLs of the M WLs;
• determine whether the first column of the memory cells passes the leakage current threshold;
• in response to the first column of the memory cells passing the leakage current threshold, selecting the negative voltage as the first negative voltage;
• and
• in response to the first column of the memory cells not passing the leakage current threshold, keep decreasing the negative voltage until the first column of the memory cells passes the leakage current threshold, wherein the leakage current verify circuit comprises:
• a sense amplifier circuit configured to compare a leakage current of the cell of the first column of the memory cells to a reference current source which serves as the leakage current threshold, and
• a buffer amplifier configured to transmit a binary signal which indicates either the passing of the first column of the memory cells or the failure of the first column of the memory cells.