Semiconductor storage device and memory system

A semiconductor storage device comprising:

• a first memory block constituted with a plurality of first strings each including a first select transistor, a plurality of first memory cell transistors, and a second select transistor in this order;
• a second memory block constituted with a plurality of second strings each including a third select transistor, a plurality of second memory cell transistors, and a fourth select transistor in this order;
• a control circuit configured to perform an erase operation on the first memory block and the second memory block;
• a first bit line connected to one end portion of one first string of the plurality of first strings;
• and
• a second bit line connected to one end portion of one second string of the plurality of second strings,
• wherein:
• when the first memory block is an open block including a memory cell transistor having a threshold of an erase level and the second memory block is a closed block not including the memory cell transistor having the threshold of the erase level, the control circuit changes setting of a first erase-verify operation that is an erase-verify operation included in the erase operation on the first memory block and setting of a second erase-verify operation that is a erase-verify operation included in the erase operation on the second memory block, and
• a voltage applied to the first bit line upon the first erase-verify operation is lower than a voltage applied to the second bit line upon the second erase-verify operation.

A semiconductor storage device comprising:

• a first memory block constituted with a plurality of first strings each including a first select transistor, a plurality of first memory cell transistors, and a second select transistor in this order;
• a second memory block constituted with a plurality of second strings each including a third select transistor, a plurality of second memory cell transistors, and a fourth select transistor in this order;
• a control circuit configured to perform an erase operation on the first memory block and the second memory block;
• a first bit line connected to one end portion of one first string of the plurality of first strings;
• a first transistor connected to the first bit line;
• a second bit line connected to one end portion of one second string of the plurality of second strings;
• and
• a second transistor connected to the second bit line,
• wherein:
• when the first memory block is an open block including a memory cell transistor having a threshold of an erase level and the second memory block is a closed block not including the memory cell transistor having the threshold of the erase level, the control circuit changes setting of a first erase-verify operation that is an erase-verify operation included in the erase operation on the first memory block and setting of a second erase-verify operation that is a erase-verify operation included in the erase operation on the second memory block, and
• a voltage applied to a gate of the first transistor upon the first erase-verify operation is lower than a voltage applied to a gate of the second transistor upon the second erase-verify operation.