Cache processes with adaptive dynamic start voltage calculation for memory devices
AssigneeIntel Corporation
InventorsXiang Yang, Ali Khakifirooz, Pranav Kalavade, Shantanu R. Rajwade
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AssigneeIntel Corporation
InventorsXiang Yang, Ali Khakifirooz, Pranav Kalavade, Shantanu R. Rajwade
Estimating the term…
A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2N−1, and Ln being one of 2N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.
A memory chip controller of a flash memory device, the memory chip controller including processing circuitry to:
A flash memory device including:
A method to be performed at a memory chip controller of a flash memory device comprising:
A non-transitory machine readable storage medium having instructions stored thereon, the instructions, when executed by a memory chip controller of a flash memory device, to cause the memory chip controller:
Dependencies are inferred from the claim text.