Staggered active bitline sensing
AssigneeIntel Corporation
InventorsAli Khakifirooz, Rezaul Haque, Dhanashree Kulkarni, Bayan Nasri
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Abstract
Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period.
Claims20
A memory chip controller comprising:
- one or more substrates;
- and
- logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable or fixed-functionality hardware, and the logic coupled to the one or more substrates is to:
- apply a first set of control signals to even bitlines in NAND memory, wherein the first set of control signals are to include an even pre-charge signal that is shared by even pre-charge transistors;
- sense voltage levels of the even bitlines during an even sensing time period;
- apply a second set of control signals to odd bitlines in the NAND memory;
- and
- sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period, and wherein the even pre-charge signal activates the even pre-charge transistors from a deactivated state during the stagger time period.
A computing system comprising:
- a system on chip (SoC);
- and
- a solid state drive coupled to the SoC, the solid state drive including NAND memory and a memory chip controller, wherein the memory chip controller includes logic to:
- apply a first set of control signals to even bitlines in the NAND memory, wherein the first set of control signals are to include an even pre-charge signal that is shared by even pre-charge transistors,
- sense voltage levels of the even bitlines during an even sensing time period,
- apply a second set of control signals to odd bitlines in the NAND memory, and
- sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period, and wherein the even pre-charge signal activates the even pre-charge transistors from a deactivated state during the stagger time period.
A method comprising:
- applying a first set of control signals to even bitlines in NAND memory, wherein the first set of control signals are to include an even pre-charge signal that is shared by even pre-charge transistors;
- sensing voltage levels of the even bitlines during an even sensing time period;
- applying a second set of control signals to odd bitlines in the NAND memory;
- and
- sensing voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period, and wherein the even pre-charge signal activates the even pre-charge transistors from a deactivated state during the stagger time period.
Dependencies are inferred from the claim text.