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US 12,224,014 B2Granted
Multi-stage data compaction in NAND
AssigneeSanDisk Technologies LLC
InventorsHarish Gajula, Bhanushankar Doni
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Abstract
Technology is disclosed herein for multi-stage data compaction. In a first data compaction stage valid data fragments from source erase block(s) are programmed into a destination erase block at two bits per memory cell. In a second data compaction stage additional valid data from the source erase block(s) is programmed into the destination erase block at two bits per memory cell. In this second stage, the same physical pages of memory cells in the destination erase block may be programmed such that each memory cell in the destination erase block is programmed to four bits.
Claims18
An apparatus comprising:
- one or more control circuits configured to connect to a three-dimensional memory structure comprising a plurality of erase blocks, each erase block comprising physical pages of memory cells, wherein the one or more control circuits are configured to:
- read first valid data from one or more source erase blocks that store data at n bits per memory cell, wherein n is a positive integer greater than 1;
- program the first valid data as m bits per memory cell in a plurality of physical pages of memory cells in a destination erase block, wherein m is a positive integer less than n;
- read second valid data from the one or more source erase blocks;
- transfer the first valid data, physical page-by-physical page, from the plurality of physical pages of memory cells in the destination erase block to first data latches associated with the destination erase block;
- transfer the second valid data, physical page-by-physical page, to second data latches associated with the destination erase block;
- and
- program the second valid data into the plurality of the physical pages of memory cells in the destination erase block physical page-by-physical page based on contents of the first data latches and the second data latches after programming the first valid data into the plurality of the physical pages such that the memory cells in the plurality of the physical pages in the destination erase block each store n bits per memory cell.
5 more elements
A method for operating a three-dimensional memory structure having erase blocks having physical pages of NAND memory cells, the method comprising:
- collecting first valid data fragments from one or more source erase blocks into a data buffer of a memory controller, wherein the one or more source erase blocks contain the first valid data fragments and invalid data fragments, wherein the physical pages of NAND memory cells in the one or more source erase blocks each store four pages of data;
- programming the first valid data fragments from the data buffer into the physical pages of NAND memory cells in a destination erase block, including programming each respective physical page of NAND memory cells with two data pages of the first valid data fragments;
- collecting second valid data fragments from the one or more source erase blocks into the data buffer of the memory controller;
- and
- programming the second valid data fragments from the data buffer into the physical pages of NAND memory cells in the destination erase block, including programming each respective physical page of NAND memory cells that was programmed with two data pages of the first valid data fragments with two additional data pages of the second valid data fragments by:
- performing an internal data load of two data pages of the first valid data fragments from the respective physical page in the destination erase block to first data latches associated with the respective physical page;
- transferring two data pages of the second valid data fragments from the data buffer of the memory controller to second data latches associated with the respective physical page;
- and
- programming the two data pages of the second valid data fragments based on content of the first data latches and the second data latches, wherein each respective physical page of NAND memory cells in the destination erase block stores four data pages of valid data from the one or more source erase blocks.
6 more elements
A non-volatile storage system comprising:
- a three-dimensional memory structure comprising NAND strings, the three-dimensional memory structure arranged as erase blocks, each erase block comprising a plurality of physical pages of NAND memory cells;
- first stage data compaction means for collecting first valid data fragments from one or more source erase blocks, wherein the one or more source erase blocks contain the first valid data fragments and invalid data fragments, wherein physical pages of NAND memory cells in the one or more source erase blocks each store four pages of data, wherein the first stage data compaction means is further for programming the first valid data fragments into the plurality of the physical pages of NAND memory cells in a destination erase block, including programming each respective physical page of NAND memory cells with two pages of the first valid data fragments;
- and
- second stage data compaction means for collecting second valid data fragments from the one or more source erase blocks, wherein the second stage data compaction means is further for programming the second valid data fragments into the plurality of the physical pages of NAND memory cells in the destination erase block after programming the first valid data fragments into the plurality of the physical pages in the destination erase block, including programming each respective physical page in the destination erase block with two additional pages of the second valid data fragments, wherein each respective physical page in the destination erase block stores four pages of valid data from the one or more source erase blocks, wherein the second stage data compaction means is further for loading the two pages of the first valid data fragments from each respective physical page of memory cells to first data latches associated with the physical pages of the memory cells, transferring the two additional pages of the second valid data fragments from a data buffer of a memory controller to second data latches associated with the physical pages, and programming the two additional pages of second valid data fragments in each respective physical page of the memory cells based on content of the first data latches and the second data latches.
1 more element
Dependencies are inferred from the claim text.