Semiconductor memory device

A semiconductor memory device, comprising:

• a memory cell array comprising a cell string and an auxiliary string, which are coupled to each other through a channel layer that is coupled to a bit line, wherein the cell string comprises a plurality of memory cells stacked along a first side portion of the channel layer and wherein the auxiliary string comprises a plurality of auxiliary transistors stacked along a second side portion of the channel layer;
• and
• a voltage supply circuit configured to apply a first pass voltage to an unselected auxiliary word line among a plurality of auxiliary word lines coupled to the plurality of auxiliary transistors and, apply a first voltage, which is less than the first pass voltage, to an unselected word line among the plurality of word lines coupled to the plurality of memory cells while applying a program voltage or a read voltage to the selected word line among the plurality of word lines.