Memory device, memory system, and method of operating the same

A method of programming a memory device, wherein the memory device comprises a memory cell array and a peripheral circuit coupled to the memory cell array, wherein memory cells in the memory cell array are arranged in rows and columns, and each memory cell is set to one of 2N levels corresponding to a piece of N-bits data, where N is an integer greater than 1, wherein the peripheral circuit comprises a plurality of page buffers coupled to bit lines, respectively, wherein the method comprises:

• storing N logical pages of first physical page corresponding to a current first programming in the N page latches, wherein the N page latches comprise (N−1) data latches in the page buffers and a cache latch coupled to a data path;
• storing second non-physical page information in a bias latch in the page buffers;
• in the process of programming the first physical page, disabling a bit line bias function to release the bias latch to replace one of the N page latches to perform a programming verification of memory states;
• releasing one of the N page latches to cache program data of one of the N logical pages of the second physical page;
• and
• in the process of programming the first physical page, storing the program data of the one of the N logical pages of the second physical page in a released page latch.

A memory system, comprising:

• a memory device, comprising:
• a memory cell array, wherein the memory cells in the memory cell array are arranged in rows and columns, and each memory cell is set to one of 2N levels corresponding to a piece of N-bits data, where N is an integer greater than 1;
• and
• a peripheral circuit coupled to the memory cell array and configured to:
• perform first programming and second programming sequentially and respectively on the memory cell array in a first physical page and a second physical page in a cache programming manner, and
• program at least a selected row of the memory cells based on N logical pages of the first physical page and the second physical page during the first programming and the second programming,
• wherein the peripheral circuit comprises page buffers respectively coupled to bit lines, each page buffer comprising:
• a bias latch, (N−1) data latches, and a cache latch coupled to a data path,
• wherein the bias latch is configured to store second non-physical page information, and the (N−1) data latches and the cache latch are configured to, during a process of programming to the N logical pages of the first physical page and the second physical page, function as N page latches to temporarily store programming data to be written into the N logical pages;
• wherein the peripheral circuit is further configured to:
• in the process of programming the first physical page, disable a bit line bias function to release the bias latch to replace one of the N page latches to perform a programming verification of memory states;
• release one of the N page latches to cache program data of one of the N logical pages of the second physical page;
• and
• in the process of programming the first physical page, store the program data of the one of the N logical pages of the second physical page in a released page latch;
• and
• a memory controller coupled to the memory device and configured to control operations of the memory device.