Synchronous input buffer control using a write shifter

A method for operating a memory device, comprising:

• disabling an input buffer;
• receiving, at the memory device, a write command;
• transmitting the write command through a write shifter of the memory device;
• after disabling the input buffer, suppressing enablement of the input buffer until the write command has reached a turn-on tap point in the write shifter;
• and
• enabling the input buffer after the write command has reached the turn-on tap point in the write shifter.

A memory device, comprising:

• a command interface configured to receive write commands from a host device;
• an input buffer configured to buffer data from the host device;
• input buffer control circuitry, comprising:
• a plurality of flip-flops configured to receive a first write command of the write commands and shift the first command through the plurality of flip-flops;
• logical OR circuitry configured to receive values from each flip-flop of the plurality of flip-flops and to cause the input buffer to be disabled after the first write command has shifted through all of the plurality of flip-flops;
• and
• control circuitry configured to prevent the input buffer from being re-enabled after the input buffer is disabled until a subsequently received second write command has shifted through a threshold number of flip-flops of the plurality of flip-flops.