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US 12,223,998 B2Granted
Apparatuses and methods for input receiver circuits and receiver masks for same
OwnerDean D. Gans, John D. Porterinventors
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Abstract
Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.
Claims29
A memory device comprising:
- a memory array;
- a command address input circuit configured to receive a command address signal, the command address input circuit comprising a command address input receiver configured to capture an input command address signal that is based at least in part on a predefined receiver mask, wherein the receiver mask has a first timing parameter associated with a first voltage level and further has a second timing parameter associated with a second voltage level, wherein the second timing parameter is greater than the first timing parameter, wherein the predefined receiver mask has a hexagonal shape;
- and
- an external clock terminal configured to receive a clock signal, wherein a center of the receiver mask is at a cross point of the clock signal.
1 more element
A method, comprising:
- receiving, at a command address input receiver of a memory device, an input command address signal;
- receiving, at an external clock terminal of the memory device, a clock signal;
- and
- capturing a pulse of the input command address signal with a time-variant voltage characteristic that is based at least in part on a receiver mask, wherein the receiver mask is a hexagonal mask shape, wherein the pulse is center aligned to device cross point of the clock signal.
1 more element
An apparatus comprising:
- a command address input circuit of a memory device configured to receive a command address input signal, wherein the command address input signal comprises a pulse defined, at least in part, by a first timing parameter indicating a length of time between intersections of the pulse with a reference voltage, a first voltage parameter indicating a peak-to-peak voltage, and second voltage parameter indicating an upper voltage and a lower voltage, wherein the second voltage parameter further corresponds to a voltage parameter of a receiver mask;
- and
- an external clock terminal configured to receive a clock signal, wherein the pulse is center aligned to a cross point of the clock signal.
A system comprising:
- a memory device;
- and
- a memory controller communicatively coupled to the memory device, the memory controller configured to:
- provide to the memory device a clock signal;
- and
- provide to the memory device a command address input signal outside a hexagonal receiver mask of the memory device, wherein the command address input signal is center aligned to a cross point of the clock signal,
- wherein the memory device is configured to capture the command address input signal.
4 more elements
An apparatus comprising:
- a memory controller communicatively coupled to a memory device, the memory controller configured to:
- provide to the memory device a clock signal;
- and
- provide to the memory device a command address input signal including a pulse defined, at least in part, by a first timing parameter indicating a length of time between intersections of the pulse with a reference voltage, a first voltage parameter indicating a peak-to-peak voltage, and second voltage parameter indicating an upper voltage and a lower voltage, wherein the second voltage parameter further corresponds to a voltage parameter of a receiver mask of the memory device, wherein the pulse is center aligned to a cross point of the clock signal.
1 more element
Dependencies are inferred from the claim text.