Address selection circuit and control method thereof, and memory

A control method of an address selection circuit, comprising:

• outputting a received regular refresh address signal or an active address signal in response to a first selection signal;
• generating, based on a row hammer address generation circuit, a second address output signal and a row hammer address redundancy identifier according to a received first selection signal, an actual active address signal, and an output signal of an address receiving circuit;
• and
• generating, based on a decoding circuit, a target address and the actual active address signal according to a received second address output signal and the row hammer address redundancy identifier:
• wherein the target address comprises at least one of an array word line address, a row hammer redundancy address, or a row hammer repair address;
• the decoding circuit comprises an initial decoding unit, a first comparison unit, a third selector, and an encoding feedback circuit;
• and the generating a target address and the actual active address signal comprises:
• performing decoding, based on the initial decoding unit according to the received second address output signal, to obtain a corresponding array word line address when the row hammer address redundancy identifier is a negative acknowledgment identifier or performing decoding according to the second address output signal, to obtain a corresponding row hammer redundancy address when the row hammer address redundancy identifier is an acknowledgment identifier;
• comparing, based on the first comparison unit, the array word line address corresponding to the received second address output signal with a prestored repair addresses in a repair address bank when the row hammer address redundancy identifier is the negative acknowledgment identifier, and outputting, when determining that the repair address bank comprises a repair address the same as the array word line address corresponding to the second address output signal, a row hammer repair address and a row hammer repair address identifier corresponding to the same repair address;
• outputting, based on the third selector, a received array word line address or the row hammer redundancy address when the row hammer repair address identifier is the negative acknowledgment identifier, and outputting the row hammer repair address when the row hammer repair address identifier is the acknowledgment identifier;
• and
• generating and outputting, based on the encoding feedback circuit, the actual active address signal to the row hammer address generation circuit according to the received second address output signal, the row hammer repair address, and a corresponding row hammer repair address identifier.