Adaptive memory registers

A method comprising:

• reading from at least one memory register, by a logic circuit configured to be coupled to a memory device that includes multiple memory blocks, at least a portion of an address associated with the multiple memory blocks, the at least a portion of the address corresponding to a refresh operation for a row of the multiple memory blocks;
• determining a quantity of row addresses between the at least a portion of the address and another row address included on a list of row addresses related to activation-based refresh operations;
• and
• adjusting the list of row addresses related to the activation-based refresh operations based on the quantity and a threshold value.

An apparatus comprising:

• logic configured to be coupled to at least one memory array, the logic configured to:
• read, from at least one memory register associated with the memory array, values that represent at least a portion of a row address of the memory array, the at least a portion of the row address corresponding to a refresh operation for a row of the memory array;
• determine a quantity of row addresses between the at least a portion of the row address and another row address included on a list of row addresses related to activation-based refresh operations;
• and
• adjust the list of row addresses related to the activation-based refresh operations, based on the quantity and a threshold value.

An apparatus, comprising:

• a memory array including multiple memory blocks;
• at least one memory register;
• and
• logic circuitry configured to:
• determine which memory blocks of the multiple memory blocks have been refreshed within a current refresh interval;
• and
• write values to respective entries of the at least one memory register associated with respective memory blocks of the multiple memory blocks, the values indicative of whether the respective memory blocks have been refreshed within the current refresh interval.

A method comprising:

• determining, by a logic circuit configured to be coupled to multiple memory blocks of a memory device, that at least some of the multiple memory blocks are to be refreshed during a current refresh interval;
• reading values from at least one memory register associated with respective memory blocks of the multiple memory blocks;
• and
• determining a portion of the multiple memory blocks that has not been refreshed within the current refresh interval, based on the values.

An apparatus comprising:

• a logic circuit configured to be coupled to at least one memory array including multiple memory blocks, the logic circuit configured to:
• determine that at least some of the multiple memory blocks are to be refreshed during a current refresh interval;
• read values of bits stored in at least one memory register associated with respective blocks of the multiple memory blocks;
• determine a portion of the multiple memory blocks that has not been refreshed within the current refresh interval, based on the values of the bits;
• and
• transmit a signal indicative of a command to execute refresh operations for the portion of the multiple memory blocks that has not been refreshed within the current refresh interval.