Display substrate and display apparatus for reducing load of clock signal line

A display apparatus, comprising a display substrate,

• wherein the display substrate comprises a base substrate comprising a display region and a peripheral region located on at least one side of the display region, and a first gate drive circuit provided on the peripheral region of the base substrate,
• wherein the first gate drive circuit comprises a first clock signal line, a second clock signal line and N shift register units that are cascaded;
• each shift register unit of the N shift register units comprises a first control circuit, a second control circuit, a first output circuit, a second output circuit and an output terminal;
• the first output circuit is electrically connected with a first node, a first clock signal terminal and the output terminal, respectively, and is configured to turn on or turn off a connection between the output terminal and the first clock signal terminal under control of a potential of the first node;
• the second output circuit is electrically connected with a second node, the output terminal and a first voltage terminal, respectively, and is configured to turn on or turn off a connection between the output terminal and the first voltage terminal under control of a potential of the second node;
• the first control circuit is electrically connected with a control terminal, the first node and a first control voltage terminal, respectively, and is configured to turn on or turn off a connection between the first node and the first control voltage terminal under control of a control signal supplied by the control terminal;
• the second control circuit is electrically connected with the control terminal, the second node and a second control voltage terminal, respectively, and is configured to turn on or turn off a connection between the second node and the second control voltage terminal under control of the control signal;
• wherein the first clock signal line and the second clock signal line extend along a first direction on the base substrate, and are configured to supply a first clock signal to the first clock signal terminal of the shift register unit, and the first clock signal line and the second clock signal line are not connected with a same shift register unit;
• the first output circuit comprises a first output transistor, an orthographic projection of the first clock signal line and an orthographic projection of the second clock signal line on the base substrate are located on a side of the first output transistor close to the display region, the orthographic projection of the second clock signal line on the base substrate is located between an orthographic projection of the first output transistor on the base substrate and the orthographic projection of the first clock signal line on the base substrate;
• and
• where N is an integer greater than 1,
• wherein the first control circuit comprises a first control transistor, and the second control circuit comprises a second control transistor,
• an active layer of the first control transistor and an active layer of the second control transistor are arranged side by side in the second direction,
• a gate electrode of the first control transistor and a gate electrode of the second control transistor are integrally formed and extend along the second direction, and
• an orthographic projection of the first output transistor on the base substrate is located between an orthographic projection of the first control transistor and the second control transistor on the base substrate and an orthographic projection of the second clock signal line on the base substrate, and an orthographic projection of the first control transistor on the base substrate is located between an orthographic projection of the second control transistor on the base substrate and the orthographic projection of the first output transistor on the base substrate.