Display substrate and display apparatus

A display substrate, comprising:

• a display area and a non-display area, wherein the display area is provided with pixel circuits arranged in an array, and the display area is divided into M partitions along a first direction;
• a pixel circuit comprises a writing transistor, an anode reset transistor, a gate control transistor, a light emitting transistor, and a first scan signal line, a second scan signal line, a third scan signal line and a light emitting signal line that extend along a second direction, wherein the first scan signal line is electrically connected with the writing transistor, the second scan signal line is electrically connected with the gate control transistor, the third scan signal line is electrically connected with the anode reset transistor, the light emitting signal line is connected with the light emitting transistor, and M is a positive integer greater than or equal to 2;
• the non-display area is provided with a light emitting driving circuit group, a control driving circuit group, a reset driving circuit group, a first light emitting clock signal line to a fourth light emitting clock signal line, a first control clock signal line to a fourth control clock signal line, and a first reset clock signal line to a fourth reset clock signal line;
• the light emitting driving circuit group comprises M light emitting driving circuits, an i-th light emitting driving circuit is connected with a light emitting signal line in a pixel circuit in an i-th partition, an odd-numbered light emitting driving circuit is electrically connected with the first light emitting clock signal line and the second light emitting clock signal line, and an even-numbered light emitting driving circuit is connected with the third light emitting clock signal line and the fourth light emitting clock signal line, where i=1, 2, . . . , M;
• and/or, the control driving circuit group comprises M control driving circuits, an i-th control driving circuit is connected with a second scan signal line in the pixel circuit in the i-th partition, an odd-numbered control driving circuit is electrically connected with the first control clock signal line and the second control clock signal line, and an even-numbered control driving circuit is connected with the third control clock signal line and the fourth control clock signal line;
• and/or, the reset driving circuit group comprises M reset driving circuits, an i-th reset driving circuit is connected with a third scan signal line in the pixel circuit in the i-th partition, an odd-numbered reset driving circuit is electrically connected with the first reset clock signal line and the second reset clock signal line, and an even-numbered reset driving circuit is connected with the third reset clock signal line and the fourth reset clock signal line.