Gate drive circuit and display panel

A display panel, comprising:

• a gate drive circuit comprising one or more shift register groups, wherein each of the shift register groups comprises N adjacent shift registers that output in sequence, N being an integer greater than or equal to 3, each of the shift registers comprises:
• a first output stage configured to output a gate drive signal;
• a frequency division control module configured to control outputting of the gate drive signal based on a refresh frequency,
• wherein a control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies;
• and
• a pixel circuit comprising a drive transistor, a compensation transistor, and a write transistor, wherein a first electrode of the compensation transistor is connected to a gate of the drive transistor, a second electrode of the compensation transistor is connected to a first electrode or a second electrode of the drive transistor, and a gate of the compensation transistor receives a gate drive signal;
• and a first electrode of the write transistor is connected to the first electrode or the second electrode of the drive transistor, a second electrode of the write transistor is connected to a data line, and a gate of the write transistor is connected to a scan line.