US 12,223,560 B2Granted

Clock architecture and method supporting PCIE clock, and medium

AssigneeSuzhou Metabrain Intelligent Technology Co., Ltd.

InventorsHaibo Wang, Zhihua Ge

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Abstract

A clock architecture supporting a PCIE clock, including a controller, a GPU, a PCIE switch, a FPGA, a first clock generator, a second clock generator, a first clock fan-out device and a second clock fan-out device; the first clock generator is configured to generate a 100 MHz homologous clock signal; the second clock generator is configured to generate a 100 MHz non-homologous clock signal; the FPGA is connected to the PCIE switch and the GPU, and configured to read clock architecture modes supported by the PCIE switch and the GPU, acquire corresponding 100 MHz clock signals according to the clock architecture modes, and fan out the acquired 100 MHz clock signals to the PCIE switch and the GPU to be used, the clock architecture modes are a homologous mode and a non-homologous mode.

Claims17

Dependent claims

A clock architecture supporting a PCIE clock, comprising:

a controller, a graphics processing unit (GPU), a programmable communication interface extension (PCIE) switch, a field-programmable gate array (FPGA), a first clock generator, a second clock generator, a first clock fan-out device and a second clock fan-out device;
wherein the first clock generator is connected to the first clock fan-out device, and is configured to generate a 100 MHz homologous clock signal;
the first clock fan-out device is connected to the controller and the FPGA, and is configured to fan out the 100 MHz homologous clock signal;
and
the second clock generator is connected to the second clock fan-out device, and is configured to generate a 100 MHz non-homologous clock signal;
the second clock fan-out device is connected to the FPGA, and is configured to fan out the 100 MHz non-homologous clock signal;
the controller is connected to the PCIE switch, the PCIE switch is connected to the GPU;
the FPGA is connected to the PCIE switch and the GPU, and is configured to read clock architecture modes supported by the PCIE switch and the GPU, acquire corresponding 100 MHz clock signals according to the clock architecture modes, and fan out the acquired 100 MHz clock signals to the PCIE switch and the GPU to be used, wherein the clock architecture modes are a homologous mode and a non-homologous mode;
wherein the FPGA is further configured to:
acquire the 100 MHz homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the homologous mode;
acquire the 100 MHz non-homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the non-homologous mode;
and
acquire the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal when the read clock architecture mode supported by the PCIE switch is the homologous mode and the read clock architecture mode supported by the GPU is the non-homologous mode.

10 more elements

A clock architecture supporting a PCIE clock, comprising a memory and one or more processors, wherein the memory is stored with computer-readable instructions that, when executed by the one or more processors, cause the one or more processors to implement operations of:

reading clock architecture modes supported by a programmable communication interface extension (PCIE) switch and a graphics processing unit (GPU), wherein the clock architecture modes are a homologous mode and a non-homologous mode;
acquiring corresponding 100 MHz clock signals according to the clock architecture modes, wherein the 100 MHz clock signals are the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal;
and
transmitting the acquired 100 MHz clock signals correspondingly to the PCIE switch and the GPU to be used;
wherein the one or more processors is further configured to implement operations of:
acquiring the 100 MHz homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the homologous mode;
acquiring the 100 MHz non-homologous clock signals when the read clock architecture modes supported by the PCIE switch and the GPU are both the non-homologous mode;
and
acquiring the 100 MHz homologous clock signal and the 100 MHz non-homologous clock signal when the read clock architecture mode supported by the PCIE switch is the homologous mode and the read clock architecture mode supported by the GPU is the non-homologous mode.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/570,597Filed 7 Jun 2022
Priority: CN 202111585044.123 Dec 2021
Published: US 2024/0273668 A115 Aug 2024
Granted: 11 Feb 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06T 1/20
General purpose image data processing: processor architectures; Processor configuration, e.g. pipelining
G06F 13/4022
Coupling between buses: using switching circuits, e.g. switching matrix, connection or expansion network
G06F 13/4291
On a serial bus, e.g. I2C bus, SPI bus: using a clocked protocol
G06F 2213/0026
Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central…:…

Family

US 2024/0273668 A1Pre-grant publication · published 15 Aug 2024
US 12,223,560 B2This patent

From the US filing history. Foreign family members aren’t listed.

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