Method and apparatus for optimizing bias error-based quantum error correction code

A quantum error correction code optimizing device implemented in hardware or in a combination of hardware and software and configured to reduce an error rate of quantum error correction codes in a biased error environment, the quantum error correction code optimizing device comprising:

• a basic information acquisition unit which acquires basic information including at least one of a physical error rate (pphy), a bias degree (η), at least one candidate lattice size, or a target logical error rate (Pf,target);
• a logical error rate estimation unit which estimates a logical error rate (Pfail) for each of the at least one candidate lattice size based on the physical error rate (pphy) and the bias degree (η) exceeding 1, the each of the at least one candidate lattice size having a rectangular form excluding a square form, wherein the square form corresponds to a bias degree (η) of 1;
• a lattice size optimization unit which determines an optimal lattice size among the at least one candidate lattice size having the rectangular form based on the estimated logical error rate (Pfail) and the target logical error rate (Pf,target);
• and
• a qubit arrangement unit which arranges a qubits based on the optimal lattice size having the rectangular form excluding the square form,
• wherein a number of the qubits arranged to the optimal lattice size is smaller than a number of qubits for a lattice size having the square form, and
• wherein the quantum error correction codes with the reduced error rate are used for processing quantum information that is applied to overcome difficulties in implementing quantum computing and quantum information communication due to noise or errors in the quantum information.