Generating and executing a control flow
OwnerKyle B. Wheeler, Richard C. Murphy +2inventors
InventorsKyle B. Wheeler, Richard C. Murphy, Troy A. Manning, Dean A. Klein
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Abstract
Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.
Claims20
A processor in memory (PIM) apparatus comprising:
- a memory device configured to receive a first plurality of mathematical operations of first control flow instructions and a second plurality of mathematical operations of second control flow instructions generated by a host, including:
- a first array of memory cells;
- a second array of memory cells;
- a first execution unit, coupled to the first array, to execute the first control flow instructions;
- a second execution unit, coupled to the second array, to execute the second control flow instructions;
- a first controller configured to control an execution of the first control flow instructions on data stored in the first array using the first execution unit;
- and
- a second controller configured to control an execution of the second control flow instructions on data stored in the second array using the second execution unit.
A system for operating a process in memory (PIM) apparatus comprising:
- a host, configured to convert host operable instructions into op-code instructions to generate control flow instructions comprising a plurality of mathematical operations;
- and
- a memory device, including:
- an array of memory cells;
- an execution unit, coupled to the array, to execute the control flow instructions;
- and
- a controller configured to control an execution of the control flow instructions on data stored in the array.
A system for operating a process in memory (PIM) apparatus comprising:
- a host configured to:
- decode host operable instructions;
- and
- dynamically generate memory operable instructions from the decoded host operable instructions;
- and
- a memory device, including:
- an array of memory cells;
- an execution unit, coupled to the array, to execute the memory operable instructions;
- and
- a controller configured to control an execution of the memory operable instructions on data stored in the array.
Dependencies are inferred from the claim text.