Apparatus and method of optimizing divergent processing in thread groups preliminary class

A data processor in which execution threads may execute program instructions to perform data processing operations, and in which execution threads may be grouped together into thread groups in which the plural execution threads of a thread group can each execute a set of instructions in lockstep;

• the data processor comprising:
• an instruction execution processing circuit operable to execute instructions to perform processing operations for execution threads executing a program, wherein the instruction execution processing circuit is configured as a plurality of execution lanes, each execution lane being operable to perform processing operations for an execution thread of a thread group;
• and
• an execution thread issuing circuit operable to issue execution threads of thread groups to the plurality of execution lanes of the instruction execution processing circuit for execution;
• wherein the execution thread issuing circuit is configured to determine whether active threads to be executed of a first thread group to perform a first operation and active threads to be executed of a second thread group to perform a second operation use different execution lanes of the plurality of execution lanes of the instruction execution processing circuit for execution in a processing cycle;
• and
• the execution thread issuing circuit is configured to issue active threads from both first and second thread groups for execution across the different execution lanes in the processing cycle when the active threads to be executed of the first thread group and active threads to be executed of the second thread group use different execution lanes of the plurality of execution lanes of the instruction execution processing circuit for execution.

A non-transitory computer readable storage medium storing software code which when executing on a data processor performs a method of operating a data processor in which execution threads may execute program instructions to perform data processing operations on data values, and in which execution threads may be grouped together into thread groups in which the plural execution threads of a thread group can each execute a set of instructions in lockstep;

• the data processor comprising:
• an instruction execution processing circuit operable to execute instructions to perform processing operations for execution threads executing a program, wherein the instruction execution processing circuit is configured as a plurality of execution lanes, each execution lane being operable to perform processing operations for an execution thread of a thread group;
• and
• an execution thread issuing circuit operable to issue execution threads of thread groups the plurality of execution lanes of the instruction execution processing circuit for execution;
• the method comprising:
• determining, using the execution thread issuing circuit, whether active threads to be executed of a first thread group to perform a first operation and active threads to be executed of a second thread group to perform a second operation use different execution lanes of the plurality of execution lanes of the instruction execution processing circuit for execution in a processing cycle;
• and
• the execution thread issuing circuit is configured to issue active threads from both first and second thread groups for execution across the different execution lanes in the processing cycle when the active threads to be executed of the first thread group and active threads to be executed of the second thread group use different execution lanes of the plurality of execution lanes of the instruction execution processing circuit for execution.