Methods and apparatus for providing mask register optimization for vector operations

An apparatus comprising:

• at least one processing core;
• and
• a vector data processing unit, operatively coupled to the at least one processing core, comprising:
• a shared scheduler queue configured to store at least both a mask type instruction and a vector type instruction in an entry thereof, wherein the mask type instruction and the vector type instruction each comprise a source operand having a corresponding shared source register bit field that indexes into a shared register space including both a mask register file and a vector register file;
• a vector data path configured to process vector data based on a queued vector type instruction;
• a mask data path configured to process a queued mask instruction that is used to control at least which of a plurality of vector processing pipelines in the vector data path are enabled to process vector data for a queued vector instruction;
• and
• shared pipeline control circuitry, operatively coupled to both the vector data path and the mask data path, operative to control either of the vector data path or the mask data path based on a type of instruction picked from the queue, and operative to use a mask register file or a vector register file depending on whether bits of the shared source register bit field identify either a mask source register or a vector source register.