Method of operating a microprocessor, related processing system and computer program product

A device, comprising:

• a memory;
• and
• one or more processors coupled to the memory, wherein the one or more processors, in operation:
• apply first combinational, arithmetic or combinational and arithmetic operations to obtained data and an expected value, the applying the first combinational, arithmetic or combinational and arithmetic operations generating a plurality of result bit sequences, wherein when the value of the obtained data corresponds to the expected value, values of generated plurality of result bit sequences are different from each other and correspond to expected values of the result bit sequences;
• apply second combinational, arithmetic or combinational and arithmetic operations to a first memory address, a second memory address, and the plurality of result bit sequences, the applying the second combinational, arithmetic or combinational and arithmetic operations generating a memory address, wherein,
• when the values of the generated plurality of result bit sequences correspond to the expected values of the result bit sequences, the generated memory address corresponds to the first memory address, and
• when one or more values of the generated plurality of result bit sequences do not correspond to the expected values of the result bit sequences, the generated memory address corresponds to the second memory address;
• jump to the generated memory address;
• and
• execute a software routine stored in an area of the memory starting at the generated memory address.

A system, comprising:

• a memory having a plurality of memory areas;
• a peripheral device;
• and
• one or more processors coupled to the memory and to the peripheral device, wherein the one or more processors, in operation:
• apply first combinational, arithmetic or combinational and arithmetic operations to obtained data and an expected value, the applying the first combinational, arithmetic or combinational and arithmetic operations generating a plurality of result bit sequences, wherein when the value of the obtained data corresponds to the expected value, values of generated plurality of result bit sequences are different from each other and correspond to expected values of the result bit sequences;
• apply second combinational, arithmetic or combinational and arithmetic operations to a first memory address, a second memory address, and the plurality of result bit sequences, the applying the second combinational, arithmetic or combinational and arithmetic operations generating a memory address, wherein,
• when the values of the generated plurality of result bit sequences correspond to the expected values of the result bit sequences, the generated memory address corresponds to the first memory address, and
• when one or more values of the generated plurality of result bit sequences do not correspond to the expected values of the result bit sequences, the generated memory address corresponds to the second memory address;
• jump to the generated memory address;
• and
• execute a software routine stored in a memory area of the plurality of memory areas starting at the generated memory address.

A non-transitory computer-readable medium having contents which configure a processing device to perform a method, the method comprising:

• applying first combinational, arithmetic or combinational and arithmetic operations to obtained data and an expected value, the applying the first combinational, arithmetic or combinational and arithmetic operations generating a plurality of result bit sequences, wherein when the value of the obtained data corresponds to the expected value, values of generated plurality of result bit sequences are different from each other and correspond to expected values of the result bit sequences;
• applying second combinational, arithmetic or combinational and arithmetic operations to a first memory address, a second memory address, and the plurality of result bit sequences, the applying the second combinational, arithmetic or combinational and arithmetic operations generating a memory address, wherein,
• when the values of the generated plurality of result bit sequences correspond to the expected values of the result bit sequences, the generated memory address corresponds to the first memory address, and
• when one or more values of the generated plurality of result bit sequences do not correspond to the expected values of the result bit sequences, the generated memory address corresponds to the second memory address;
• jumping to the generated memory address;
• and
• executing a software routine stored in an area of the memory starting at the generated memory address.