Neural network device for neural network operation, operating method of the neural network device, and application processor including the same

A method of operating a neural network device, the operating method comprising:

• configuring the neural network device to perform both floating point and integer operations;
• receiving a plurality of data pairs;
• performing a floating point operation when the plurality of data pairs have a floating point format;
• performing an integer operation when the plurality of data pairs have an integer format;
• and
• storing final data generated through the floating point operation or the integer operation in a memory,
• wherein performing the floating point operation comprises:
• obtaining a plurality of fraction multiplication results that respectively correspond to the plurality of data pairs using a floating point multiplier,
• performing an align shift of the plurality of fraction multiplication results based on a maximum value identified from a plurality of exponent addition results that respectively correspond to the plurality of data pairs using an align shifter,
• adding upper bits, but not lower bits, of the aligned plurality of fraction multiplication results using a first add circuit included in an adder,
• adding lower bits, but not upper bits, of the aligned plurality of fraction multiplication results using a second add circuit included in the adder,
• adding the plurality of fraction multiplication results using a post adder wherein first cumulative data is generated,
• detecting a first leading one by right shifting upper bits of the first cumulative data using the post adder, and
• detecting a second leading one by right shifting lower bits of the first cumulative data that exclude the upper bits of the first cumulative data using the post adder, and
• wherein performing the integer operation comprises:
• obtaining a plurality of integer multiplication results that respectively correspond to the plurality of data pairs using an integer multiplier, and
• adding the plurality of integer multiplication results using the adder wherein second cumulative data is generated.

An application processor, comprising:

• a neural network device that includes a floating point multiplier, an integer multiplier, an adder, a first post adder and a memory,
• wherein the neural network device performs
• a first dot product operation on a plurality of floating point data pairs or
• a second dot product operation on a plurality of integer data pairs, wherein,
• in the first dot product operation, the neural network device
• obtains a plurality of fraction multiplication results from the plurality of floating point data pairs, respectively, using the floating point multiplier,
• adds the plurality of fraction multiplication results using the adder wherein first cumulative data is generated,
• detects a first leading one by right shifting upper bits of the first cumulative data using the first post adder,
• detects a second leading one by right shifting lower bits of the first cumulative data that exclude the upper bits of the first cumulative data using the first post adder, and
• stores the first cumulative data in the memory, wherein
• in the second dot product operation, the neural network device
• obtains a plurality of integer multiplication results from the plurality of integer data pairs, respectively, using the floating point multiplier and the integer multiplier,
• adds the plurality of integer multiplication results using the adder wherein second cumulative data is generated, and
• stores the second cumulative data in the memory,
• wherein the adder comprises:
• a first add circuit that adds upper bits, but not lower bits, of the plurality of fraction multiplication results in the first dot product operation;
• and
• a second add circuit that adds lower bits, but not upper bits, of the plurality of fraction multiplication results in the first dot product operation, or adds the plurality of integer multiplication results in the second dot product operation.