Systems, methods, and computer program products for transistor compact modeling using artificial neural networks

A system for analyzing performance of a semiconductor device, the system comprising:

• a processor;
• and
• a memory that stores computer readable code that, when executed, causes the processor to perform operations comprising:
• providing training data comprising input state values and training capacitance values to a neural network executing on a computer system;
• processing the input state values through the neural network to generate modeled charge values;
• converting the modeled charge values to modeled capacitance values;
• determining, by the computer system, whether the training capacitance values of the training data are within a threshold value of the modeled capacitance values utilizing a loss function that omits the modeled charge values;
• in response to determining that the training capacitance values of the training data are within the threshold value of the modeled capacitance values, converting, by the computer system, the neural network to a circuit simulation code to generate a converted neural network;
• using the converted neural network to simulate behavior of a test semiconductor device to generate simulation output;
• determining, by the computer system, whether a turnaround time of the generation of the simulation output is satisfactory;
• and
• in response to determining that the turnaround time is not satisfactory, decreasing, by the computer system, the size of the neural network and repeating the processing of the input state values through the neural network.

A computer program product, comprising:

• a non-transitory computer readable storage medium storing computer readable program code that, when executed by a processor of an electronic device, causes the processor to perform operations comprising:
• providing training data comprising input state values and training capacitance values to a neural network executing on a computer system;
• processing the input state values through the neural network to generate modeled charge values;
• converting the modeled charge values to modeled capacitance values;
• determining, by the computer system, whether the training capacitance values of the training data are within a threshold value of the modeled capacitance values utilizing a loss function that omits the modeled charge values;
• in response to determining that the training capacitance values of the training data are within the threshold value of the modeled capacitance values, converting, by the computer system, the neural network to a circuit simulation code to generate a converted neural network;
• using the converted neural network to simulate behavior of a test semiconductor device to generate simulation output;
• determining, by the computer system, whether a turnaround time of the generation of the simulation output is satisfactory;
• and
• in response to determining that the turnaround time is not satisfactory, decreasing, by the computer system, the size of the neural network and repeating the processing of the input state values through the neural network.