Memory-aligned access operations

An apparatus, comprising:

• a memory device comprising a plurality of physical pages of non-volatile memory cells;
• and
• a controller coupled with the memory device and configured to cause the apparatus to:
• transmit, to a host system, an indication of a data size corresponding to a quantity of physical pages that are addressable by individual first-level pages of a first-level page table for mapping logical addresses to respective physical pages of the plurality of physical pages, wherein a target packet size for an application at the host system is based at least in part on the data size;
• receive, from the host system based at least in part on transmitting the indication, a set of data associated with the application and a command to write the set of data to the memory device, a size of the set of data being the target packet size and the command comprising a logical address for the set of data;
• identify, based at least in part on the logical address, a second-level entry of a second-level page table, wherein the second-level entry of the second-level page table points to a first-level page of the first-level page table, and wherein first-level entries of the first-level page map a set of logical addresses to a set of physical addresses, the set of logical addresses comprising the logical address;
• and
• write, based at least in part on identifying the second-level entry, the set of data to the set of physical addresses beginning at a first physical address corresponding to a lowest logical address mapped to by a lowest level page of the first-level page table and ending at a second physical address corresponding to a highest logical address mapped to by the lowest level page of the first-level page table.