Memory interface for initalizing memory and method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsRaghu Vamsi Krishna Talanki, Archita Khare, Rahul Tarikere Ravikumar, Jinin So, Jonggeon Lee
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Abstract
A memory interface for interfacing with a memory device includes a control circuit configured to determine whether a trigger event has occurred for initializing one or more memory locations in the memory device, and initialize the one or more memory locations in the memory device with pre-defined data upon determining the trigger event has occurred.
Claims19
A memory interface for interfacing with a memory device, the memory interface comprising:
- a control circuit configured to determine whether a trigger event has occurred for initializing one or more memory locations in the memory device, and initialize the one or more memory locations in the memory device with pre-defined data upon determining the trigger event has occurred,
- wherein the pre-defined data is run-time data from an application running on a computer system including the memory device,
- wherein the pre-defined data is stored in one or more registers associated with the computer system.
A method for interfacing with a memory device, the method comprising:
- determining, by a control circuit of a memory interface, whether a trigger event has occurred for initializing one or more memory locations in the memory device;
- and
- initializing, by the control circuit, the one or more memory locations in the memory device with pre-defined data related upon determining the trigger event has occurred,
- wherein the pre-defined data is run-time data from an application running on a computer system including the memory device,
- wherein the pre-defined data is stored in one or more registers associated with the computer system.
A memory interface for interfacing with a memory device, the memory interface comprising:
- a memory controller connected to the memory device;
- a cache connected to the memory controller;
- and
- a central processing unit (CPU) connected to the cache via a data bus and connected to the memory controller via signal line separate from the data bus,
- wherein the memory controller initializes one or more memory locations of the memory device in response to receiving a trigger signal from the CPU via the signal line.
Dependencies are inferred from the claim text.