Memory chip, operating method thereof, and judging method

A memory chip comprising:

• at least two groups of nonvolatile registers, wherein each group of the nonvolatile registers comprises a flag register and at least one data register, and stored data of each of flag registers is configured to indicate at least one storage state of the at least one data register in a same group of the nonvolatile registers;
• an obtaining module, wherein the obtaining module is configured to obtain the stored data of at least one of the flag registers;
• a judgment module, wherein the judgment module is configured to judge whether the stored data of the at least one of the flag registers is random code;
• a selective erasure module, wherein the selective erasure module is configured to erase all of the nonvolatile registers in response to the stored data of the at least one of the flag registers being the random code;
• a first reading unit, wherein the first reading unit is configured to read the stored data of the flag registers from a first group of the nonvolatile registers to a last group of the nonvolatile registers according to an address sequence;
• a first judgment unit, wherein the first judgment unit is configured to judge whether the stored data of the flag register in a current group of the nonvolatile registers is 0x00;
• in response to the stored data of the flag register in the current group of the nonvolatile registers being non-0x00, judging whether the stored data of the flag register in the current group of the nonvolatile registers is 0xFF;
• and in response to the stored data of the flag register in the current group of the nonvolatile registers being 0xFF, storing a storage address of the current group of the nonvolatile registers;
• and
• a first selective erasure unit, wherein the first selective erasure unit is configured to record the stored data of the at least one data register in a last group of the nonvolatile registers that is in a non-writable state to a buffer, and to erase all of the nonvolatile registers in response to a fact that the stored data of the flag register in the current group of the nonvolatile registers is non-0xFF.

An operating method of a memory chip, comprising steps of:

• constructing the memory chip comprising at least two groups of nonvolatile registers, wherein each group of the nonvolatile registers comprises a flag register and at least one data register, and stored data of each of flag registers is configured to indicate at least one storage state of the at least one data register in a same group of the nonvolatile registers;
• obtaining the stored data of at least one of the flag registers;
• judging whether the stored data of the at least one of the flag registers is random code, wherein the random code are data being non-0x00 and being non-0xFF, wherein 0x00 represents binary data of 00000000, 0xFF represents binary data of 11111111, the non-0x00 represents binary data other than 00000000, and the non-0xFF represents binary data other than 11111111;
• and
• erasing all of the nonvolatile registers in response to the stored data of the at least one of the flag registers being the random code;
• wherein after the step of judging whether the stored data of the at least one of the flag registers is the random code, the operating method further comprises steps of:
• reading the stored data of each of the flag registers in the nonvolatile registers according to an address sequence from a first group of the nonvolatile registers to a last group of the nonvolatile registers, in response to the stored data of each of the flag registers in all of the nonvolatile registers being not the random code;
• judging whether the stored data of the flag register in a current group of the nonvolatile registers is 0xFF;
• judging whether the current group of the nonvolatile registers is the last group of the nonvolatile registers, in response to the stored data of the flag register in the current group of the nonvolatile registers being non-0xFF;
• recording the stored data of the at least one data register in the last group of the nonvolatile registers that is in a non-writable state to a buffer before erasing all of the nonvolatile registers, in response to the current group of the nonvolatile registers being the last group of the nonvolatile registers;
• and
• writing data to be written to the first group of the nonvolatile registers, wherein the data to be written comprises flag data, unnecessary updated data of the stored data stored in the buffer, and data to be updated of the stored data stored in the buffer;
• the flag data is written to the flag register in the first group of the nonvolatile registers, the unnecessary updated data of the stored data stored in the buffer is correspondingly written to at least one data bit that do not need to be updated in the first group of the nonvolatile registers, and the data to be updated of the stored data stored in the buffer is correspondingly written to at least one data bit that needs to be updated in the first group of the nonvolatile registers.