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US 12,223,100 B2Granted
Hardware protection of inline cryptographic processor
AssigneeTexas Instruments Incorporated
InventorsAmritpal S. Mundra, William C. Wallace
Life of this patent
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Abstract
A real time, on-the-fly data encryption system is operable to encrypt and decrypt data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with its own separate encryption capability, or no encryption at all. Data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. Protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location.
Claims16
A data encryption system comprising:
- an encryption engine including a plurality of encryption cores, each configured to perform at least one of multiple types of cryptographic operations, including an encryption operation, a decryption operation, and a message authentication operation;
- a memory interface configured to write encrypted data received from one or more of the plurality of encryption cores to a memory, and further configured to provide encrypted data received from the memory to one or more of the plurality of encryption cores;
- a command buffer configured to associate each transaction of multiple transactions of the data encryption system with a corresponding response of multiple responses by the memory interface;
- and
- a scheduler configured to determine that a command specifies one of the multiple types of cryptographic operations based on a mode of a region of the memory which is specified by an address of the command.
2 more elements
A computing system comprising:
- an encryption engine including a plurality of encryption cores, each configured to perform at least one of multiple types of cryptographic operations, including an encryption operation, a decryption operation, and a message authentication operation;
- a memory including a plurality of regions including a first memory region and a second memory region;
- a memory interface coupled to the memory and configured to write encrypted data received from one or more of the plurality of encryption cores to the memory, and further configured to provide encrypted data received from the memory to one or more of the plurality of encryption cores;
- a command buffer configured to associate each transaction of multiple transactions of the data encryption system with a corresponding response of multiple responses by the memory interface;
- and
- a scheduler configured to determine that a command specifies one type of cryptographic operation of the multiple types of cryptographic operations based on a mode of a region of the external memory which is specified by an address of the command.
3 more elements
Dependencies are inferred from the claim text.