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AssigneeGroq, Inc.
InventorsDennis Charles Abts, Jonathan Alexander Ross, John Thompson, Gregory Michael Thorson
Estimating the term…
Embodiments are directed to a processor having a functional slice architecture. The processor is divided into tiles (or functional units) organized into a plurality of functional slices. The functional slices are configured to perform specific operations within the processor, which includes memory slices for storing operand data and arithmetic logic slices for performing operations on received operand data (e.g., vector processing, matrix manipulation). The processor includes a plurality of functional slices of a module type, each functional slice having a plurality of tiles. The processor further includes a plurality of data transport lanes for transporting data in a direction indicated in a corresponding instruction. The processor also includes a plurality of instruction queues, each instruction queue associated with a corresponding functional slice of the plurality of functional slices, wherein the instructions in the instruction queues comprise a functional slice specific operation code.
A processor comprising a plurality of functional modules configured to deterministically process data using a process selected from a) storing data received from or providing stored data to a transport structure, b) transposing data received from the transport structure, c) performing Boolean operations on data received from the transport structure, and d) performing multiplication operations on data received from the transport structure, each of the plurality of functional modules having a plurality of functional units controlled by instructions issued by an instruction control unit (ICU) and having a plurality of functional module specific Instruction Set Architectures (ISAs), each ISA of the functional module specific ISAs being configured to define operating instructions for each of the plurality of functional units in each functional module of the plurality of functional modules, and wherein the functional module specific ISAs provide temporal information comprising one of a functional delay (dfunc) and an instruction-operand skew (dskew).
A deterministic processor system comprising a compiler and a processor having a plurality of functional modules and a module specific instruction set architecture (ISA) that exposes temporal information about each instruction in the module specific ISA to allow the compiler precise control of each instruction's dispatch time from one of a plurality of instruction queues (IQ), each IQ managed by an instruction control unit (ICU), wherein each instruction in the module specific ISA is augmented with at least one of following temporal parameters:
A deterministic processor system comprising:
Dependencies are inferred from the claim text.