A method for performing a sequence of data operations in a data processing system having a target central processing unit (CPU), an interconnect circuit separate from the target CPU, and a plurality of data processing circuits, the method comprising:
- generating, by the target CPU, a current prefix, the current prefix including a current sequentially ordered list of the plurality of data processing circuits corresponding to the sequence of data operations;
- receiving, at the interconnect circuit, the current prefix from the target CPU;
- receiving, at the interconnect circuit, from an input data source a current data payload to be processed;
- generating, by the interconnect circuit, a current data packet by prepending the current prefix to the current data payload;
- and
- sequentially sending, by the interconnect circuit, the current data packet to the plurality of data processing circuits by:
- i) determining, by the interconnect circuit, based on a next entry in the current sequentially ordered list included in the current prefix of the current data packet, a one of the plurality of data processing circuits associated with the next entry;
- ii) removing, by the interconnect circuit, the next entry and an associated set of parameters from the current prefix to generate an updated prefix;
- iii) replacing, by the interconnect circuit, the current prefix with the updated prefix in the current data packet;
- iv) sending, by the interconnect circuit, the current data packet to the one of the plurality of data processing circuits associated with the next entry in the current sequentially ordered list included in the current prefix, together with the associated set of parameters;
- v) receiving, by the interconnect circuit, from the one of the plurality of data processing circuits an updated data packet including the updated prefix and a processed data payload generated by the one of the plurality of data processing circuits using the current data payload and the associated set of parameters;
- vi) in response to determining that a next entry in the updated prefix is associated with any of the plurality of data processing circuits, repeating, by the interconnect circuit, steps i) to v) using the updated data packet as the current data packet with the updated prefix being the current prefix;
- and
- vii) in response to determining that the next entry in the updated prefix is associated with a data destination, removing, by the interconnect circuit, the next entry from the updated prefix in the updated data packet and sending, by the interconnect circuit, the updated data packet with the next entry removed to the data destination;
- receiving, by the one of the plurality of data processing circuits, the current data packet and the associated set of parameters from the interconnect circuit;
- performing, by the one of the plurality of data processing circuits, a data operation on the current data payload included in the current data packet to generate a processed data payload;
- and
- sending, by the one of the plurality of data processing circuits, the updated data packet including the processed data payload and the updated prefix to the interconnect circuit;
- wherein:
- each entry in the current sequentially ordered list comprises an address of the one of the plurality of data processing circuits associated with that entry;
- the plurality of data processing circuits comprise two or more data processing circuits configured to perform a same data operation;
- a first address in the current sequentially ordered list is a virtual address associated with the same data operation performed by the two or more data processing circuits;
- and
- when the next entry in the current sequentially ordered list comprises the first address, sending the current data packet to the one of the plurality of data processing circuits associated with the next entry in the current sequentially ordered list comprises:
- determining, by the interconnect circuit, an available one of the two or more data processing circuits configured to perform the same data operation;
- replacing the first address in the next entry with an actual address of the available one of the two or more data processing circuits configured to perform the same data operation;
- and
- sending the current data packet to the available one of the two or more data processing circuits.