Method for transferring data between a first digital domain and a second digital domain, and corresponding system on a chip

A system on a chip, comprising:

• a first digital domain configured to be reinitialized by a first reinitialization signal;
• a second digital domain;
• and
• an interface circuit including at least one transfer element in the first digital domain;
• wherein the interface circuit is configured to transfer data from said at least one transfer element to the second digital domain;
• and
• wherein said at least one transfer element is configured to not be reinitialized by the first reinitialization signal;
• wherein the interface circuit includes:
• a starting register out of said at least one transfer element;
• a destination register in the second digital domain;
• and
• a synchronization circuit in the first digital domain;
• wherein the interface circuit is configured to transfer data from the starting register to the destination register upon command of a control signal transmitted by the synchronization circuit;
• and
• wherein the synchronization circuit is configured to not be reinitialized by the first reinitialization signal;
• wherein the first digital domain is configured to be clocked by a first clock signal at a first frequency and the second digital domain is configured to be clocked by a second clock signal at a second frequency lower than the first frequency;
• and
• wherein the first digital domain is configured to communicate the data to be transferred on an input of the starting register and to communicate the control signal to the synchronization circuit at least one cycle of the first clock signal after said data;
• and
• wherein the starting register is configured to input the data to be transferred in a single cycle of the first clock signal and then preserve said data independently of said input.

A method for transferring data between at least a first digital domain and a second digital domain of a system on a chip, comprising:

• transferring data from at least one transfer element in the first digital domain to the second digital domain;
• and
• in response to a first reinitialization signal, causing a reinitialization of the first digital domain, but not causing a reinitialization of said at least one transfer element;
• wherein transferring data comprises adapting a signal with a signal adaptation element out of said at least one transfer element, and transferring a link establishment conditioning signal between the first digital domain and the second digital domain;
• and
• wherein adapting the signal comprises inputting, in a starting register, a value of the link establishment conditioning signal in a single cycle of a first clock signal and preserving said value afterward.

A method for transferring data between at least a first digital domain and a second digital domain of a system on a chip comprising:

• clocking the first digital domain by a first clock signal at a first frequency;
• clocking the second digital domain by a second clock signal at a second frequency lower than the first frequency;
• transferring data from at least one transfer element in the first digital domain to the second digital domain;
• and
• in response to a first reinitialization signal, causing a reinitialization of the first digital domain, but not causing a reinitialization of said at least one transfer element;
• wherein transferring data comprises transferring data from a starting register out of said at least one transfer element to a destination register in the second digital domain in response to a control signal transmitted by a synchronization circuit of the first digital domain, wherein the first reinitialization signal does not cause a reinitialization of the synchronization circuit;
• communicating the data to be transferred on an input of the starting register;
• communicating the control signal to the synchronization circuit at least one cycle of the first clock signal after said data;
• and
• wherein transferring the data comprises inputting, by the starting register, the data to be transferred in a single cycle of the first clock signal and preserving said data afterward, independently of said input.